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3c13e3289a
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Merge branch 'new_structure'
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2026-03-02 19:38:21 +01:00 |
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4e3521e94a
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Added missing signal modules
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2026-03-02 19:28:36 +01:00 |
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50f71a2985
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Added new master checker and changed to synchronous reset checks
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2026-03-02 18:02:47 +01:00 |
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628972ccaa
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New slave checker and updated gpio and gpio_banks
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2026-03-02 13:48:30 +01:00 |
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a6a5c6ea3f
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Made timer synthesizable
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2026-03-01 21:11:08 +01:00 |
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5b940758b6
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Added formal verification set to timer internally
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2026-03-01 21:00:57 +01:00 |
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abe0668787
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new timer
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2026-03-01 17:19:46 +01:00 |
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7b46ae5e87
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Some cleanup and added formal for the banks and timer
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2026-03-01 14:12:12 +01:00 |
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8289b0d090
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Added wb formal script and added other sby tasks
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2026-03-01 13:52:41 +01:00 |
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cf483decad
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Added everything from the other system
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2026-02-28 21:52:06 +01:00 |
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907f244b24
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Added libjtag_wb_bridge
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2026-02-28 18:39:50 +01:00 |
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cf7e03b9fe
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Added some stuff from modem and added formal
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2026-02-28 18:23:39 +01:00 |
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fa641b1eab
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Initial commit
Added nco_q15
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2026-02-28 13:52:08 +01:00 |
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105dbed8e4
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Added back in the jtag bridge
Now talking over the bus instead of using dpram
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2026-02-27 17:39:43 +01:00 |
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6f680377db
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jtag memory selectable
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2026-02-27 16:09:33 +01:00 |
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3a9b2acf9e
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New wishbone-jtag bridge
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2026-02-27 15:56:56 +01:00 |
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838204653a
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TImer working with tests
TODO: think of other way of shifting in data. Bit errors make uploading difficult
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2026-02-25 22:01:28 +01:00 |
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3a3c951409
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Added timer, still wip
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2026-02-25 20:54:12 +01:00 |
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f2f9644830
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Added qerv files
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2026-02-25 20:52:07 +01:00 |
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13f72e698f
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jtag memory interface working
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2026-02-25 16:14:37 +01:00 |
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9930ce4461
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Working CPP way of writing data
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2026-02-24 16:40:17 +01:00 |
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8f4e887b9d
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Added JTAG interface with testbench
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2026-02-23 15:37:49 +01:00 |
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20cfece6e3
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Added soclet with gpio banks to top
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2026-02-22 20:00:42 +01:00 |
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a97028c2ba
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cleanup
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2026-02-22 18:49:03 +01:00 |
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5e951f9b61
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Working SERV cpu
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2026-02-22 18:48:17 +01:00 |
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ac6aea90b6
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Merge branch 'master' of ssh://git.joppeb.nl:222/joppe/fpga_modem
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2026-02-22 16:07:34 +01:00 |
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dc946cd793
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Moved serv to own tree
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2026-02-22 16:03:21 +01:00 |
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a261264fda
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Added serv and made a blinky testbench for it
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2026-02-21 19:24:18 +01:00 |
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Joppe Blondel
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49b8a77480
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Combined all sigmadelta things to one input block
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2025-10-19 20:03:51 +02:00 |
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Joppe Blondel
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165faefa59
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Added decimation
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2025-10-19 17:26:09 +02:00 |
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Joppe Blondel
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771fa58769
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Added K IIR lpf filter
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2025-10-19 17:02:29 +02:00 |
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Joppe Blondel
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b2858ac5ee
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Added mul tb and fixed
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2025-10-19 16:18:40 +02:00 |
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Joppe Blondel
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eb7caaf2c5
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Added PLL/clock generator and SD RC model
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2025-10-19 15:36:55 +02:00 |
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Joppe Blondel
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3b04f3a6be
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Added lvds and sampler
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2025-10-08 18:01:03 +02:00 |
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Jojojoppe
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324bb108e3
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Added planahead script and fixed conversion
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2025-10-06 16:49:28 +02:00 |
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Jojojoppe
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06ef70e1ee
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Improved NCO: 200MHz
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2025-10-06 16:25:40 +02:00 |
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Jojojoppe
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1e9d7b7680
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Got rid of ftw_we and tested on hw with freq sweep
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2025-10-05 23:42:51 +02:00 |
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Jojojoppe
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83cc449c6f
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Using remotesyn and added NCO
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2025-10-05 23:20:25 +02:00 |
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Jojojoppe
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639541728f
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Added decimator
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2025-10-01 21:52:21 +02:00 |
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Jojojoppe
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e0151d093f
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Added sampler and RC model
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2025-10-01 21:15:20 +02:00 |
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Jojojoppe
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ee58fccba4
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Added pll to simulation
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2025-10-01 17:24:53 +02:00 |
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Jojojoppe
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42e9bd0a0a
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initial commit
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2025-10-01 16:40:05 +02:00 |
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