joppe/fpga_modem
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13f72e698f4d56e1466ca5a0c775b1e8db6a1639
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Joppe Blondel 13f72e698f jtag memory interface working
2026-02-25 16:14:37 +01:00
boards/mimas_v1
Added JTAG interface with testbench
2026-02-23 15:37:49 +01:00
rtl
jtag memory interface working
2026-02-25 16:14:37 +01:00
scripts
Working CPP way of writing data
2026-02-24 16:40:17 +01:00
sim
jtag memory interface working
2026-02-25 16:14:37 +01:00
sw
Added JTAG interface with testbench
2026-02-23 15:37:49 +01:00
tools
jtag memory interface working
2026-02-25 16:14:37 +01:00
.gitignore
Added JTAG interface with testbench
2026-02-23 15:37:49 +01:00
.gitmodules
Moved serv to own tree
2026-02-22 16:03:21 +01:00
project.cfg
jtag memory interface working
2026-02-25 16:14:37 +01:00
Description
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738 KiB
Languages
Verilog 87.2%
C++ 7.2%
Python 2.7%
SystemVerilog 1.2%
Assembly 0.6%
Other 1%