Joppe Blondel e0769f0c0d Test with modem connected

2026-03-05 19:49:44 +01:00

cores

Test with modem connected

2026-03-05 19:49:44 +01:00

fusesoc_libraries

new timer

2026-03-01 17:19:46 +01:00

modem

Test with modem connected

2026-03-05 19:49:44 +01:00

.gitignore

Signal scope

2026-03-05 15:06:09 +01:00

.gitmodules

new timer

2026-03-01 17:19:46 +01:00

capture1.png

Test with modem connected

2026-03-05 19:49:44 +01:00

capture2.csv

Test with modem connected

2026-03-05 19:49:44 +01:00

capture2.png

Test with modem connected

2026-03-05 19:49:44 +01:00

check_formal.sh

Added formal verification set to timer internally

2026-03-01 21:00:57 +01:00

fusesoc.conf

Added everything from the other system

2026-02-28 21:52:06 +01:00

xilinx_fusesoc.sh

new timer

2026-03-01 17:19:46 +01:00

Description

No description provided

1.1 MiB

Languages

Verilog 69.4%

C++ 15.9%

Python 8.2%

SystemVerilog 2%

C 1.3%

Other 3.2%