Joppe Blondel a6a5c6ea3f Made timer synthesizable

2026-03-01 21:11:08 +01:00

cores

Made timer synthesizable

2026-03-01 21:11:08 +01:00

fusesoc_libraries

new timer

2026-03-01 17:19:46 +01:00

.gitignore

new timer

2026-03-01 17:19:46 +01:00

.gitmodules

new timer

2026-03-01 17:19:46 +01:00

check_formal.sh

Added formal verification set to timer internally

2026-03-01 21:00:57 +01:00

fusesoc.conf

Added everything from the other system

2026-02-28 21:52:06 +01:00

xilinx_fusesoc.sh

new timer

2026-03-01 17:19:46 +01:00

Description

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738 KiB

Languages

Verilog 87.2%

C++ 7.2%

Python 2.7%

SystemVerilog 1.2%

Assembly 0.6%

Other 1%