joppe/fpga_modem
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abe0668787357f68ce25db37144588a838c2cb62
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Joppe Blondel abe0668787 new timer
2026-03-01 17:19:46 +01:00
cores
new timer
2026-03-01 17:19:46 +01:00
fusesoc_libraries
new timer
2026-03-01 17:19:46 +01:00
.gitignore
new timer
2026-03-01 17:19:46 +01:00
.gitmodules
new timer
2026-03-01 17:19:46 +01:00
check_formal.sh
new timer
2026-03-01 17:19:46 +01:00
fusesoc.conf
Added everything from the other system
2026-02-28 21:52:06 +01:00
xilinx_fusesoc.sh
new timer
2026-03-01 17:19:46 +01:00
Description
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738 KiB
Languages
Verilog 87.2%
C++ 7.2%
Python 2.7%
SystemVerilog 1.2%
Assembly 0.6%
Other 1%