Joppe Blondel 838204653a TImer working with tests ...

TODO: think of other way of shifting in data. Bit errors make uploading difficult

2026-02-25 22:01:28 +01:00

boards/mimas_v1

Added JTAG interface with testbench

2026-02-23 15:37:49 +01:00

rtl

TImer working with tests

2026-02-25 22:01:28 +01:00

scripts

Working CPP way of writing data

2026-02-24 16:40:17 +01:00

sim

TImer working with tests

2026-02-25 22:01:28 +01:00

sw

TImer working with tests

2026-02-25 22:01:28 +01:00

tools

jtag memory interface working

2026-02-25 16:14:37 +01:00

.gitignore

Added JTAG interface with testbench

2026-02-23 15:37:49 +01:00

.gitmodules

Moved serv to own tree

2026-02-22 16:03:21 +01:00

project.cfg

Added timer, still wip

2026-02-25 20:54:12 +01:00

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738 KiB

Languages

Verilog 87.2%

C++ 7.2%

Python 2.7%

SystemVerilog 1.2%

Assembly 0.6%

Other 1%