joppe/fpga_modem
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fa641b1eabf3ed133e37d3f7c7ec2d86a5962d7e
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Joppe Blondel fa641b1eab Initial commit 
Added nco_q15
2026-02-28 13:52:08 +01:00
cores/nco_q15
Initial commit
2026-02-28 13:52:08 +01:00
.gitignore
Initial commit
2026-02-28 13:52:08 +01:00
fusesoc.conf
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2026-02-28 13:52:08 +01:00
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738 KiB
Languages
Verilog 87.2%
C++ 7.2%
Python 2.7%
SystemVerilog 1.2%
Assembly 0.6%
Other 1%