joppe/fpga_modem
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cf7e03b9fe70250fad3d14f64000bbc6908355f5
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Joppe Blondel cf7e03b9fe Added some stuff from modem and added formal
2026-02-28 18:23:39 +01:00
cores
Added some stuff from modem and added formal
2026-02-28 18:23:39 +01:00
.gitignore
Initial commit
2026-02-28 13:52:08 +01:00
fusesoc.conf
Initial commit
2026-02-28 13:52:08 +01:00
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1.1 MiB
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Verilog 69.4%
C++ 15.9%
Python 8.2%
SystemVerilog 2%
C 1.3%
Other 3.2%