Joppe Blondel b2858ac5ee Added mul tb and fixed

2025-10-19 16:18:40 +02:00

boards/mimas_v1

Added PLL/clock generator and SD RC model

2025-10-19 15:36:55 +02:00

rtl

Added mul tb and fixed

2025-10-19 16:18:40 +02:00

scripts

Added planahead script and fixed conversion

2025-10-06 16:49:28 +02:00

sim

Added mul tb and fixed

2025-10-19 16:18:40 +02:00

.gitignore

Using remotesyn and added NCO

2025-10-05 23:20:25 +02:00

project.cfg

Added mul tb and fixed

2025-10-19 16:18:40 +02:00

Description

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738 KiB

Languages

Verilog 87.2%

C++ 7.2%

Python 2.7%

SystemVerilog 1.2%

Assembly 0.6%

Other 1%