Joppe Blondel 5e951f9b61 Working SERV cpu

2026-02-22 18:48:17 +01:00

boards/mimas_v1

Working SERV cpu

2026-02-22 18:48:17 +01:00

rtl

Working SERV cpu

2026-02-22 18:48:17 +01:00

scripts

Working SERV cpu

2026-02-22 18:48:17 +01:00

sim

Working SERV cpu

2026-02-22 18:48:17 +01:00

sw

Working SERV cpu

2026-02-22 18:48:17 +01:00

.gitignore

Using remotesyn and added NCO

2025-10-05 23:20:25 +02:00

.gitmodules

Moved serv to own tree

2026-02-22 16:03:21 +01:00

project.cfg

Working SERV cpu

2026-02-22 18:48:17 +01:00

Description

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1.1 MiB

Languages

Verilog 69.4%

C++ 15.9%

Python 8.2%

SystemVerilog 2%

C 1.3%

Other 3.2%