Joppe Blondel 20cfece6e3 Added soclet with gpio banks to top

2026-02-22 20:00:42 +01:00

boards/mimas_v1

Working SERV cpu

2026-02-22 18:48:17 +01:00

rtl

Added soclet with gpio banks to top

2026-02-22 20:00:42 +01:00

scripts

Added soclet with gpio banks to top

2026-02-22 20:00:42 +01:00

sim

Added soclet with gpio banks to top

2026-02-22 20:00:42 +01:00

sw

Added soclet with gpio banks to top

2026-02-22 20:00:42 +01:00

.gitignore

Using remotesyn and added NCO

2025-10-05 23:20:25 +02:00

.gitmodules

Moved serv to own tree

2026-02-22 16:03:21 +01:00

project.cfg

Added soclet with gpio banks to top

2026-02-22 20:00:42 +01:00

Description

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738 KiB

Languages

Verilog 87.2%

C++ 7.2%

Python 2.7%

SystemVerilog 1.2%

Assembly 0.6%

Other 1%