joppe/fpga_modem
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
3 Commits 4 Branches 0 Tags
907f244b248d56b0e3ea893683cb71f24250fc8f
Go to file
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
Joppe Blondel 907f244b24 Added libjtag_wb_bridge
2026-02-28 18:39:50 +01:00
cores
Added libjtag_wb_bridge
2026-02-28 18:39:50 +01:00
.gitignore
Initial commit
2026-02-28 13:52:08 +01:00
fusesoc.conf
Initial commit
2026-02-28 13:52:08 +01:00
Description
No description provided
738 KiB
Languages
Verilog 87.2%
C++ 7.2%
Python 2.7%
SystemVerilog 1.2%
Assembly 0.6%
Other 1%