joppe/fpga_modem
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Joppe Blondel 907f244b24 Added libjtag_wb_bridge
2026-02-28 18:39:50 +01:00
cores
Added libjtag_wb_bridge
2026-02-28 18:39:50 +01:00
.gitignore
Initial commit
2026-02-28 13:52:08 +01:00
fusesoc.conf
Initial commit
2026-02-28 13:52:08 +01:00
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1.1 MiB
Languages
Verilog 69.4%
C++ 15.9%
Python 8.2%
SystemVerilog 2%
C 1.3%
Other 3.2%