joppe/fpga_modem
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
4 Commits 4 Branches 0 Tags
639541728f5576ea3924c4b32184d1ee7abeaab0
Go to file
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
Jojojoppe 639541728f Added decimator
2025-10-01 21:52:21 +02:00
CON
Added sampler and RC model
2025-10-01 21:15:20 +02:00
HW
Added decimator
2025-10-01 21:52:21 +02:00
IP
Added sampler and RC model
2025-10-01 21:15:20 +02:00
scripts
Added sampler and RC model
2025-10-01 21:15:20 +02:00
SIM
Added decimator
2025-10-01 21:52:21 +02:00
.gitignore
initial commit
2025-10-01 16:40:05 +02:00
modem.gprj
Added sampler and RC model
2025-10-01 21:15:20 +02:00
modem.gprj.user
Added sampler and RC model
2025-10-01 21:15:20 +02:00
Description
No description provided
738 KiB
Languages
Verilog 87.2%
C++ 7.2%
Python 2.7%
SystemVerilog 1.2%
Assembly 0.6%
Other 1%