joppe/fpga_modem
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639541728f5576ea3924c4b32184d1ee7abeaab0
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Jojojoppe 639541728f Added decimator
2025-10-01 21:52:21 +02:00
CON
Added sampler and RC model
2025-10-01 21:15:20 +02:00
HW
Added decimator
2025-10-01 21:52:21 +02:00
IP
Added sampler and RC model
2025-10-01 21:15:20 +02:00
scripts
Added sampler and RC model
2025-10-01 21:15:20 +02:00
SIM
Added decimator
2025-10-01 21:52:21 +02:00
.gitignore
initial commit
2025-10-01 16:40:05 +02:00
modem.gprj
Added sampler and RC model
2025-10-01 21:15:20 +02:00
modem.gprj.user
Added sampler and RC model
2025-10-01 21:15:20 +02:00
Description
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438 KiB
Languages
Verilog 86.5%
SystemVerilog 7.5%
Python 4.8%
Tcl 0.9%
Shell 0.3%