Joppe Blondel 3a3c951409 Added timer, still wip

2026-02-25 20:54:12 +01:00

boards/mimas_v1

Added JTAG interface with testbench

2026-02-23 15:37:49 +01:00

rtl

Added timer, still wip

2026-02-25 20:54:12 +01:00

scripts

Working CPP way of writing data

2026-02-24 16:40:17 +01:00

sim

Added timer, still wip

2026-02-25 20:54:12 +01:00

sw

Added timer, still wip

2026-02-25 20:54:12 +01:00

tools

jtag memory interface working

2026-02-25 16:14:37 +01:00

.gitignore

Added JTAG interface with testbench

2026-02-23 15:37:49 +01:00

.gitmodules

Moved serv to own tree

2026-02-22 16:03:21 +01:00

project.cfg

Added timer, still wip

2026-02-25 20:54:12 +01:00

Description

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1.1 MiB

Languages

Verilog 69.4%

C++ 15.9%

Python 8.2%

SystemVerilog 2%

C 1.3%

Other 3.2%