Joppe Blondel 3c13e3289a Merge branch 'new_structure'

2026-03-02 19:38:21 +01:00

cores

Added missing signal modules

2026-03-02 19:28:36 +01:00

fusesoc_libraries

new timer

2026-03-01 17:19:46 +01:00

.gitignore

new timer

2026-03-01 17:19:46 +01:00

.gitmodules

new timer

2026-03-01 17:19:46 +01:00

check_formal.sh

Added formal verification set to timer internally

2026-03-01 21:00:57 +01:00

fusesoc.conf

Added everything from the other system

2026-02-28 21:52:06 +01:00

xilinx_fusesoc.sh

new timer

2026-03-01 17:19:46 +01:00

Description

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770 KiB

Languages

Verilog 71.6%

C++ 18%

Python 3.1%

SystemVerilog 2.3%

C 1.4%

Other 3.5%