Joppe Blondel 3a9b2acf9e New wishbone-jtag bridge

2026-02-27 15:56:56 +01:00

boards/mimas_v1

Added JTAG interface with testbench

2026-02-23 15:37:49 +01:00

rtl

New wishbone-jtag bridge

2026-02-27 15:56:56 +01:00

scripts

Working CPP way of writing data

2026-02-24 16:40:17 +01:00

sim

New wishbone-jtag bridge

2026-02-27 15:56:56 +01:00

sw

New wishbone-jtag bridge

2026-02-27 15:56:56 +01:00

tools

New wishbone-jtag bridge

2026-02-27 15:56:56 +01:00

.gitignore

Added JTAG interface with testbench

2026-02-23 15:37:49 +01:00

.gitmodules

Moved serv to own tree

2026-02-22 16:03:21 +01:00

project.cfg

New wishbone-jtag bridge

2026-02-27 15:56:56 +01:00

Description

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738 KiB

Languages

Verilog 87.2%

C++ 7.2%

Python 2.7%

SystemVerilog 1.2%

Assembly 0.6%

Other 1%