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joppe
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fpga_modem
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a261264fdaba6d3f4efcc00dab7b37a7eb8593c0
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Joppe Blondel
a261264fda
Added serv and made a blinky testbench for it
2026-02-21 19:24:18 +01:00
boards
/mimas_v1
Using remotesyn and added NCO
2025-10-05 23:20:25 +02:00
external
Added serv and made a blinky testbench for it
2026-02-21 19:24:18 +01:00
rtl
Added serv and made a blinky testbench for it
2026-02-21 19:24:18 +01:00
scripts
Added planahead script and fixed conversion
2025-10-06 16:49:28 +02:00
sim
Added serv and made a blinky testbench for it
2026-02-21 19:24:18 +01:00
sw
/blinky
Added serv and made a blinky testbench for it
2026-02-21 19:24:18 +01:00
.gitignore
Using remotesyn and added NCO
2025-10-05 23:20:25 +02:00
.gitmodules
Added serv and made a blinky testbench for it
2026-02-21 19:24:18 +01:00
project.cfg
Added serv and made a blinky testbench for it
2026-02-21 19:24:18 +01:00
Description
No description provided
1.1
MiB
Languages
Verilog
69.4%
C++
15.9%
Python
8.2%
SystemVerilog
2%
C
1.3%
Other
3.2%
