Joppe Blondel 49b8a77480 Combined all sigmadelta things to one input block

2025-10-19 20:03:51 +02:00

boards/mimas_v1

Added PLL/clock generator and SD RC model

2025-10-19 15:36:55 +02:00

rtl

Combined all sigmadelta things to one input block

2025-10-19 20:03:51 +02:00

scripts

Added K IIR lpf filter

2025-10-19 17:02:29 +02:00

sim

Combined all sigmadelta things to one input block

2025-10-19 20:03:51 +02:00

.gitignore

Using remotesyn and added NCO

2025-10-05 23:20:25 +02:00

project.cfg

Combined all sigmadelta things to one input block

2025-10-19 20:03:51 +02:00

Description

No description provided

1.1 MiB

Languages

Verilog 69.4%

C++ 15.9%

Python 8.2%

SystemVerilog 2%

C 1.3%

Other 3.2%