joppe/fpga_modem
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771fa587699c1baa35d391834013720f359faf43
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Joppe Blondel 771fa58769 Added K IIR lpf filter
2025-10-19 17:02:29 +02:00
boards/mimas_v1
Added PLL/clock generator and SD RC model
2025-10-19 15:36:55 +02:00
rtl
Added K IIR lpf filter
2025-10-19 17:02:29 +02:00
scripts
Added K IIR lpf filter
2025-10-19 17:02:29 +02:00
sim
Added K IIR lpf filter
2025-10-19 17:02:29 +02:00
.gitignore
Using remotesyn and added NCO
2025-10-05 23:20:25 +02:00
project.cfg
Added K IIR lpf filter
2025-10-19 17:02:29 +02:00
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738 KiB
Languages
Verilog 87.2%
C++ 7.2%
Python 2.7%
SystemVerilog 1.2%
Assembly 0.6%
Other 1%