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joppe
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fpga_modem
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1e9d7b7680b7b70b2387ae6b7e1ca814cdecc79f
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Jojojoppe
1e9d7b7680
Got rid of ftw_we and tested on hw with freq sweep
2025-10-05 23:42:51 +02:00
boards
/mimas_v1
Using remotesyn and added NCO
2025-10-05 23:20:25 +02:00
rtl
Got rid of ftw_we and tested on hw with freq sweep
2025-10-05 23:42:51 +02:00
scripts
Using remotesyn and added NCO
2025-10-05 23:20:25 +02:00
sim
/tb
Got rid of ftw_we and tested on hw with freq sweep
2025-10-05 23:42:51 +02:00
.gitignore
Using remotesyn and added NCO
2025-10-05 23:20:25 +02:00
project.cfg
Using remotesyn and added NCO
2025-10-05 23:20:25 +02:00
Description
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1.1
MiB
Languages
Verilog
69.4%
C++
15.9%
Python
8.2%
SystemVerilog
2%
C
1.3%
Other
3.2%
