joppe/fpga_modem
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ee58fccba4a42172f79850c8e1f69b4797d22803
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Jojojoppe ee58fccba4 Added pll to simulation
2025-10-01 17:24:53 +02:00
CON
Added pll to simulation
2025-10-01 17:24:53 +02:00
HW
Added pll to simulation
2025-10-01 17:24:53 +02:00
IP/gw_pllvr
Added pll to simulation
2025-10-01 17:24:53 +02:00
scripts
Added pll to simulation
2025-10-01 17:24:53 +02:00
SIM
Added pll to simulation
2025-10-01 17:24:53 +02:00
.gitignore
initial commit
2025-10-01 16:40:05 +02:00
modem.gprj
Added pll to simulation
2025-10-01 17:24:53 +02:00
modem.gprj.user
Added pll to simulation
2025-10-01 17:24:53 +02:00
Description
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738 KiB
Languages
Verilog 87.2%
C++ 7.2%
Python 2.7%
SystemVerilog 1.2%
Assembly 0.6%
Other 1%