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fpga_modem
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Joppe Blondel
ac6aea90b6
Merge branch 'master' of ssh://git.joppeb.nl:222/joppe/fpga_modem
2026-02-22 16:07:34 +01:00
boards
/mimas_v1
Added PLL/clock generator and SD RC model
2025-10-19 15:36:55 +02:00
rtl
Merge branch 'master' of ssh://git.joppeb.nl:222/joppe/fpga_modem
2026-02-22 16:07:34 +01:00
scripts
Added K IIR lpf filter
2025-10-19 17:02:29 +02:00
sim
Merge branch 'master' of ssh://git.joppeb.nl:222/joppe/fpga_modem
2026-02-22 16:07:34 +01:00
sw
/blinky
Moved serv to own tree
2026-02-22 16:03:21 +01:00
.gitignore
Using remotesyn and added NCO
2025-10-05 23:20:25 +02:00
.gitmodules
Moved serv to own tree
2026-02-22 16:03:21 +01:00
project.cfg
Merge branch 'master' of ssh://git.joppeb.nl:222/joppe/fpga_modem
2026-02-22 16:07:34 +01:00
Description
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1.1
MiB
Languages
Verilog
69.4%
C++
15.9%
Python
8.2%
SystemVerilog
2%
C
1.3%
Other
3.2%
