joppe/fpga_modem
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  • 49b8a77480 Combined all sigmadelta things to one input block master Joppe Blondel 2025-10-19 20:03:51 +02:00
  • 165faefa59 Added decimation Joppe Blondel 2025-10-19 17:19:08 +02:00
  • 85d9979e2d Added decimation remotesyn Joppe Blondel 2025-10-19 17:19:08 +02:00
  • 771fa58769 Added K IIR lpf filter Joppe Blondel 2025-10-19 17:02:29 +02:00
  • b2858ac5ee Added mul tb and fixed Joppe Blondel 2025-10-19 16:18:40 +02:00
  • eb7caaf2c5 Added PLL/clock generator and SD RC model Joppe Blondel 2025-10-19 15:36:55 +02:00
  • 3b04f3a6be Added lvds and sampler Joppe Blondel 2025-10-08 18:01:03 +02:00
  • 324bb108e3 Added planahead script and fixed conversion Jojojoppe 2025-10-06 16:49:28 +02:00
  • 06ef70e1ee Improved NCO: 200MHz Jojojoppe 2025-10-06 16:25:40 +02:00
  • 1e9d7b7680 Got rid of ftw_we and tested on hw with freq sweep Jojojoppe 2025-10-05 23:42:51 +02:00
  • 83cc449c6f Using remotesyn and added NCO Jojojoppe 2025-10-05 23:20:25 +02:00
  • 639541728f Added decimator Jojojoppe 2025-10-01 21:52:21 +02:00
  • e0151d093f Added sampler and RC model Jojojoppe 2025-10-01 21:15:20 +02:00
  • ee58fccba4 Added pll to simulation Jojojoppe 2025-10-01 17:24:53 +02:00
  • 42e9bd0a0a initial commit Jojojoppe 2025-10-01 16:40:05 +02:00