Joppe Blondel 3b04f3a6be Added lvds and sampler

2025-10-08 18:01:03 +02:00

boards/mimas_v1

Using remotesyn and added NCO

2025-10-05 23:20:25 +02:00

rtl

Added lvds and sampler

2025-10-08 18:01:03 +02:00

scripts

Added planahead script and fixed conversion

2025-10-06 16:49:28 +02:00

sim

Added lvds and sampler

2025-10-08 18:01:03 +02:00

.gitignore

Using remotesyn and added NCO

2025-10-05 23:20:25 +02:00

project.cfg

Added lvds and sampler

2025-10-08 18:01:03 +02:00

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1.1 MiB

Languages

Verilog 69.4%

C++ 15.9%

Python 8.2%

SystemVerilog 2%

C 1.3%

Other 3.2%