joppe/fpga_modem
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e0151d093f92d2cd3f4c3f60e1b28e83ec0751c6
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Jojojoppe e0151d093f Added sampler and RC model
2025-10-01 21:15:20 +02:00
CON
Added sampler and RC model
2025-10-01 21:15:20 +02:00
HW
Added sampler and RC model
2025-10-01 21:15:20 +02:00
IP
Added sampler and RC model
2025-10-01 21:15:20 +02:00
scripts
Added sampler and RC model
2025-10-01 21:15:20 +02:00
SIM
Added sampler and RC model
2025-10-01 21:15:20 +02:00
.gitignore
initial commit
2025-10-01 16:40:05 +02:00
modem.gprj
Added sampler and RC model
2025-10-01 21:15:20 +02:00
modem.gprj.user
Added sampler and RC model
2025-10-01 21:15:20 +02:00
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1.1 MiB
Languages
Verilog 69.4%
C++ 15.9%
Python 8.2%
SystemVerilog 2%
C 1.3%
Other 3.2%