Trigger selection

Now talking over the bus instead of using dpram

.gitignore

@@ -1,2 +1,3 @@
 build/
 out/
+*__pycache__*

cores/primitive/lvds_comparator/lvds_comparator_spartan6.v

@@ -5,10 +5,10 @@ module lvds_comparator_spartan6_impl (
 );
     IBUFDS #(
         .DIFF_TERM("FALSE"),
-        .IOSTANDARD("LVDS33")
+        .IOSTANDARD("LVDS_33")
     ) lvds_buf (
         .O(o),
         .I(a),
         .IB(b)
     );
-endmodule
+endmodule

cores/signal/sd_adc_q15/rtl/sd_adc_q15.v

@@ -38,7 +38,7 @@ module sd_adc_q15 #(
     );
 
     lpf_iir_q15_k #(
-        .K(10)
+        .K(6)
     ) lpf (
         .i_clk(i_clk_15), .i_rst_n(i_rst_n),
         .i_x_q15(raw_sample_q15),
@@ -46,7 +46,8 @@ module sd_adc_q15 #(
     );
 
     decimate_by_r_q15 #(
-        .R(375), // 15MHz/375 = 40KHz
+        .R(200), // 15MHz/200 = 75KHz
+        // .R(375), // 15MHz/375 = 40KHz
         .CNT_W(10)
     ) decimate (
         .i_clk(i_clk_15), .i_rst_n(i_rst_n),

cores/signal/signal_scope/rtl/signal_scope_q15.v

@@ -0,0 +1,240 @@
+`include "clog2.vh"
+
+module signal_scope_q15 #(
+    parameter depth = 2**12,
+    parameter chain = 1
+)(
+    input wire i_clk,
+    input wire i_rst,
+    input wire [15:0] i_signal_a,
+    input wire i_signal_valid_a,
+    input wire [15:0] i_signal_b,
+    input wire i_signal_valid_b,
+    input wire [15:0] i_signal_c,
+    input wire i_signal_valid_c,
+    input wire [15:0] i_signal_d,
+    input wire i_signal_valid_d
+);
+    localparam aw = `CLOG2(depth);
+    localparam [aw-1:0] depth_last = depth-1;
+    localparam [31:0] reg_base_addr = 32'h8000_0000;
+    localparam [3:0] reg_control = 4'h0;
+    localparam [3:0] reg_status = 4'h1;
+    localparam [3:0] reg_trig_val = 4'h2;
+
+    (* ram_style = "block" *) reg [16*4-1:0] mem[depth-1:0];
+    reg [aw-1:0] counter;
+    reg count_enable;
+    reg arm_req;
+    reg trigger_enable;
+    reg scope_armed;
+    reg scope_triggered;
+    reg capture_done;
+    reg [1:0] trigger_channel;
+    reg [15:0] trig_val;
+    reg [15:0] trigger_prev;
+    reg trigger_prev_valid;
+
+    reg [15:0] signal_a;
+    reg [15:0] signal_b;
+    reg [15:0] signal_c;
+    reg [15:0] signal_d;
+    reg signal_a_pending;
+    reg signal_b_pending;
+    reg signal_c_pending;
+    reg signal_d_pending;
+
+    wire [31:0] wb_adr;
+    wire [31:0] wb_dat;
+    wire [3:0] wb_sel;
+    wire wb_we;
+    wire wb_cyc;
+    wire wb_stb;
+    reg [31:0] wb_rdt;
+    reg wb_ack;
+    wire [aw-1:0] wb_mem_idx = wb_adr[aw+2:3];
+    wire wb_is_reg = (wb_adr[31:28] == reg_base_addr[31:28]);
+    wire [3:0] wb_reg_idx = wb_adr[5:2];
+    reg [15:0] trigger_sample;
+    reg trigger_sample_valid;
+
+    jtag_wb_bridge #(
+        .chain(chain),
+        .byte_aligned(0)
+    ) jtag_scope_bridge (
+        .i_clk(i_clk),
+        .i_rst(i_rst),
+        .o_wb_adr(wb_adr),
+        .o_wb_dat(wb_dat),
+        .o_wb_sel(wb_sel),
+        .o_wb_we(wb_we),
+        .o_wb_cyc(wb_cyc),
+        .o_wb_stb(wb_stb),
+        .i_wb_rdt(wb_rdt),
+        .i_wb_ack(wb_ack),
+        .o_cmd_reset()
+    );
+
+    always @(*) begin
+        case(trigger_channel)
+            2'd0: begin
+                trigger_sample = i_signal_a;
+                trigger_sample_valid = i_signal_valid_a;
+            end
+            2'd1: begin
+                trigger_sample = i_signal_b;
+                trigger_sample_valid = i_signal_valid_b;
+            end
+            2'd2: begin
+                trigger_sample = i_signal_c;
+                trigger_sample_valid = i_signal_valid_c;
+            end
+            default: begin
+                trigger_sample = i_signal_d;
+                trigger_sample_valid = i_signal_valid_d;
+            end
+        endcase
+    end
+
+    always @(posedge i_clk) begin
+        if(i_rst) begin
+            counter <= {aw{1'b0}};
+            count_enable <= 1'b0;
+            arm_req <= 1'b0;
+            trigger_enable <= 1'b0;
+            scope_armed <= 1'b0;
+            scope_triggered <= 1'b0;
+            capture_done <= 1'b0;
+            trigger_channel <= 2'd0;
+            wb_ack <= 1'b0;
+            wb_rdt <= 32'b0;
+            trig_val <= 16'h0000;
+            trigger_prev <= 16'h0000;
+            trigger_prev_valid <= 1'b0;
+            signal_a <= 0;
+            signal_b <= 0;
+            signal_c <= 0;
+            signal_d <= 0;
+            signal_a_pending <= 1'b0;
+            signal_b_pending <= 1'b0;
+            signal_c_pending <= 1'b0;
+            signal_d_pending <= 1'b0;
+        end else begin
+
+            // Sample signals
+            if(i_signal_valid_a) begin
+                signal_a <= i_signal_a;
+                signal_a_pending <= 1'b1;
+            end
+            if(i_signal_valid_b) begin
+                signal_b <= i_signal_b;
+                signal_b_pending <= 1'b1;
+            end
+            if(i_signal_valid_c) begin
+                signal_c <= i_signal_c;
+                signal_c_pending <= 1'b1;
+            end
+            if(i_signal_valid_d) begin
+                signal_d <= i_signal_d;
+                signal_d_pending <= 1'b1;
+            end
+
+            // Trigger on selected channel rising across trig_val.
+            if(scope_armed && trigger_enable && !count_enable && trigger_sample_valid) begin
+                if(trigger_prev_valid &&
+                   ($signed(trigger_prev) < $signed(trig_val)) &&
+                   ($signed(trigger_sample) >= $signed(trig_val))) begin
+                    count_enable <= 1'b1;
+                    scope_triggered <= 1'b1;
+                end
+                trigger_prev <= trigger_sample;
+                trigger_prev_valid <= 1'b1;
+            end
+
+            // Arm/rearm capture. If trigger is disabled, start capture immediately.
+            if(arm_req) begin
+                counter <= {aw{1'b0}};
+                count_enable <= !trigger_enable;
+                scope_armed <= 1'b1;
+                scope_triggered <= !trigger_enable;
+                capture_done <= 1'b0;
+                trigger_prev_valid <= 1'b0;
+                signal_a_pending <= 1'b0;
+                signal_b_pending <= 1'b0;
+                signal_c_pending <= 1'b0;
+                signal_d_pending <= 1'b0;
+            end
+
+            // Write one full 4-channel frame at a time for maximum BRAM throughput.
+            if(count_enable && signal_a_pending && signal_b_pending && signal_c_pending && signal_d_pending) begin
+                if(counter <= depth_last) begin
+                    mem[counter] <= {signal_a, signal_b, signal_c, signal_d};
+                    counter <= counter + {{(aw-1){1'b0}}, 1'b1};
+                    if(counter == depth_last) begin
+                        count_enable <= 1'b0;
+                        scope_armed <= 1'b0;
+                        capture_done <= 1'b1;
+                    end
+                end else begin
+                    count_enable <= 1'b0;
+                    scope_armed <= 1'b0;
+                    capture_done <= 1'b1;
+                end
+                signal_a_pending <= 1'b0;
+                signal_b_pending <= 1'b0;
+                signal_c_pending <= 1'b0;
+                signal_d_pending <= 1'b0;
+            end
+
+            // WB slave response: register window + capture memory window.
+            arm_req <= 1'b0;
+            wb_ack <= wb_cyc & wb_stb & !wb_ack;
+            if(wb_cyc & wb_stb & !wb_ack) begin
+                if(wb_we) begin
+                    wb_rdt <= 32'b0;
+                    if(wb_is_reg) begin
+                        // Keep register write decode in one case so new writable registers
+                        // can be added without touching memory-path logic.
+                        case(wb_reg_idx)
+                            reg_control: begin
+                                if(wb_sel[0]) begin
+                                    // Bit 0: write-1 pulse to arm/rearm scope.
+                                    if(wb_dat[0])
+                                        arm_req <= 1'b1;
+                                    // Bit 1: trigger enable.
+                                    trigger_enable <= wb_dat[1];
+                                    // Bits [3:2]: trigger channel (0=a,1=b,2=c,3=d).
+                                    trigger_channel <= wb_dat[3:2];
+                                end
+                            end
+                            reg_trig_val: begin
+                                if(wb_sel[0]) trig_val[7:0] <= wb_dat[7:0];
+                                if(wb_sel[1]) trig_val[15:8] <= wb_dat[15:8];
+                            end
+                            default: begin
+                            end
+                        endcase
+                    end
+                end else begin
+                    if(wb_is_reg) begin
+                        case(wb_reg_idx)
+                            // [3:2]=trigger_channel, [1]=trigger_enable, [0]=arm(write pulse only/read 0).
+                            reg_control: wb_rdt <= {28'b0, trigger_channel, trigger_enable, 1'b0};
+                            // [0]=triggered, [1]=capturing, [2]=armed, [3]=done
+                            reg_status: wb_rdt <= {28'b0, capture_done, scope_armed, count_enable, scope_triggered};
+                            reg_trig_val: wb_rdt <= {16'b0, trig_val};
+                            default: wb_rdt <= 32'b0;
+                        endcase
+                    end else if(wb_mem_idx <= depth_last) begin
+                        // A single frame is 64-bit: {a, b, c, d}. WB reads low/high 32-bit halves.
+                        wb_rdt <= wb_adr[2] ? mem[wb_mem_idx][63:32] : mem[wb_mem_idx][31:0];
+                    end else begin
+                        wb_rdt <= 32'b0;
+                    end
+                end
+            end
+
+        end
+    end
+
+endmodule

cores/signal/signal_scope/signal_scope_q15.core

@@ -0,0 +1,32 @@
+CAPI=2:
+
+name: joppeb:signal:signal_scope_q15:1.0
+description: Simple signal capture buffer for debug/scope use
+
+filesets:
+    rtl:
+        depend:
+            - joppeb:util:clog2
+            - joppeb:wb:jtag_wb_bridge
+        files:
+            - rtl/signal_scope_q15.v
+        file_type: verilogSource
+
+targets:
+    default:
+        filesets:
+            - rtl
+        toplevel: signal_scope_q15
+        parameters:
+            - depth
+            - chain
+
+parameters:
+    depth:
+        datatype: int
+        description: Number of samples stored in internal memory
+        paramtype: vlogparam
+    chain:
+        datatype: int
+        description: JTAG chain identifier 
+        paramtype: vlogparam

cores/signal/signal_scope/tool/capture_plot.py

@@ -0,0 +1,243 @@
+#!/usr/bin/env python3
+import argparse
+import sys
+import time
+from pathlib import Path
+
+import matplotlib.pyplot as plt
+
+MEM_BASE = 0x00000000
+REG_BASE = 0x80000000
+REG_CONTROL = REG_BASE + 0x00
+REG_STATUS = REG_BASE + 0x04
+REG_TRIG_VAL = REG_BASE + 0x08
+
+
+def _add_bridge_module_path() -> None:
+    here = Path(__file__).resolve()
+    bridge_tool = here.parents[3] / "wb" / "jtag_wb_bridge" / "tool"
+    sys.path.insert(0, str(bridge_tool))
+
+
+def _to_signed(value: int, width: int) -> int:
+    if width <= 0:
+        return value
+    sign_bit = 1 << (width - 1)
+    mask = (1 << width) - 1
+    value &= mask
+    return value - (1 << width) if (value & sign_bit) else value
+
+
+def parse_args() -> argparse.Namespace:
+    parser = argparse.ArgumentParser(
+        description="Arm signal_scope once, dump samples over JTAG WB, and plot them."
+    )
+    parser.add_argument("--port", type=int, default=0, help="Digilent device index")
+    parser.add_argument("--chain", type=int, default=1, help="JTAG USER chain")
+    parser.add_argument("--selector", type=str, default=None, help="Optional device selector string")
+    parser.add_argument(
+        "--depth",
+        type=int,
+        default=1024,
+        help="Number of scope frames to read (must match RTL depth)",
+    )
+    parser.add_argument(
+        "--wait-s",
+        type=float,
+        default=0.05,
+        help="Seconds to wait after arm/dearm before reading",
+    )
+    parser.add_argument(
+        "--trigger-value",
+        type=lambda x: int(x, 0),
+        default=None,
+        help="Optional trigger threshold (16-bit, signal_a rising crossing). If omitted, triggering is disabled.",
+    )
+    parser.add_argument(
+        "--trigger-channel",
+        choices=["a", "b", "c", "d"],
+        default="a",
+        help="Trigger source channel when triggering is enabled",
+    )
+    parser.add_argument(
+        "--unsigned",
+        action="store_true",
+        help="Plot samples as unsigned (default: signed two's complement)",
+    )
+    parser.add_argument("--out", type=str, default=None, help="Optional PNG output path")
+    parser.add_argument(
+        "--dump-csv",
+        type=str,
+        default=None,
+        help="Optional CSV output path with columns: index,value",
+    )
+    parser.add_argument(
+        "--interactive",
+        action="store_true",
+        help="Keep running: press Enter to recapture/replot in the same window",
+    )
+    parser.add_argument(
+        "--continuous",
+        action="store_true",
+        help="Keep running and recapture continuously without waiting for Enter",
+    )
+    return parser.parse_args()
+
+
+def capture_once(bridge, args: argparse.Namespace) -> list[tuple[int, int, int, int]]:
+    samples = []
+    frame_count = args.depth
+    trigger_channel_map = {"a": 0, "b": 1, "c": 2, "d": 3}
+    trigger_channel = trigger_channel_map[args.trigger_channel]
+    if args.trigger_value is None:
+        print("[signal_scope] Arming scope with trigger disabled...")
+        bridge.write32(REG_CONTROL, 0x1)  # bit0: arm pulse, bit1: trigger enable=0
+    else:
+        trig_val = args.trigger_value & 0xFFFF
+        print(
+            f"[signal_scope] Config trigger: trig_val=0x{trig_val:04x}, "
+            f"source=signal_{args.trigger_channel} rising"
+        )
+        bridge.write32(REG_TRIG_VAL, trig_val)
+        print("[signal_scope] Arming scope with trigger enabled...")
+        bridge.write32(REG_CONTROL, 0x3 | (trigger_channel << 2))  # bit0: arm, bit1: trig_en, bits[3:2]: channel
+
+        # Wait until the new arm command is active, then wait for its trigger event.
+        while (bridge.read32(REG_STATUS) & 0x4) == 0:
+            time.sleep(0.001)
+
+        print("[signal_scope] Waiting for trigger...")
+        while True:
+            status = bridge.read32(REG_STATUS)
+            if status & 0x1:
+                break
+            time.sleep(0.001)
+
+    if args.wait_s > 0:
+        print(f"[signal_scope] Waiting {args.wait_s:.3f}s for capture to complete...")
+        time.sleep(args.wait_s)
+
+    print(f"[signal_scope] Reading back {frame_count} frames...")
+    for idx in range(frame_count):
+        base = MEM_BASE + idx * 8
+        low = bridge.read32(base)
+        high = bridge.read32(base + 4)
+
+        ch_a = low & 0xFFFF
+        ch_b = (low >> 16) & 0xFFFF
+        ch_c = high & 0xFFFF
+        ch_d = (high >> 16) & 0xFFFF
+        if not args.unsigned:
+            ch_a = _to_signed(ch_a, 16)
+            ch_b = _to_signed(ch_b, 16)
+            ch_c = _to_signed(ch_c, 16)
+            ch_d = _to_signed(ch_d, 16)
+        samples.append((ch_a, ch_b, ch_c, ch_d))
+        if idx and (idx % max(1, frame_count // 10) == 0):
+            pct = (100 * idx) // frame_count
+    print(f"[signal_scope] Read complete: {len(samples)} frames")
+    return samples
+
+
+def write_csv(samples: list[tuple[int, int, int, int]], csv_path: Path) -> None:
+    print(f"[signal_scope] Writing CSV to {csv_path}...")
+    with csv_path.open("w", encoding="utf-8") as f:
+        f.write("index,ch_a,ch_b,ch_c,ch_d\n")
+        for idx, values in enumerate(samples):
+            f.write(f"{idx},{values[0]},{values[1]},{values[2]},{values[3]}\n")
+    print(f"Wrote CSV: {csv_path}")
+
+
+def plot_samples(ax, samples: list[tuple[int, int, int, int]], args: argparse.Namespace, capture_idx: int) -> None:
+    series = [[], [], [], []]
+    for ch_a, ch_b, ch_c, ch_d in samples:
+        series[0].append(ch_a)
+        series[1].append(ch_b)
+        series[2].append(ch_c)
+        series[3].append(ch_d)
+
+    ax.cla()
+    ax.plot(series[0], linewidth=1, label="ch_d")
+    ax.plot(series[1], linewidth=1, label="ch_c")
+    ax.plot(series[2], linewidth=1, label="ch_b")
+    ax.plot(series[3], linewidth=1, label="ch_a")
+    ax.set_title(f"signal_scope_q15 capture #{capture_idx} (depth={args.depth}, chain={args.chain})")
+    ax.set_xlabel("Sample")
+    ax.set_ylabel("Value")
+    if not args.unsigned:
+        ax.set_ylim([-2**15, 2**15])
+    ax.grid(True, alpha=0.3)
+    ax.legend(loc="upper right")
+
+
+def main() -> int:
+    args = parse_args()
+
+    if args.depth <= 0:
+        raise ValueError("--depth must be > 0")
+
+    _add_bridge_module_path()
+    from libjtag_wb_bridge.jtag_bridge import JtagBridge  # pylint: disable=import-error
+
+    print(
+        f"[signal_scope] Starting capture: port={args.port}, chain={args.chain}, "
+        f"depth={args.depth}, selector={args.selector!r}"
+    )
+
+    with JtagBridge() as bridge:
+        print("[signal_scope] Opening JTAG bridge...")
+        if args.selector:
+            bridge.open_selector(args.selector, port=args.port, chain=args.chain)
+        else:
+            bridge.open(port=args.port, chain=args.chain)
+        print("[signal_scope] Bridge opened")
+
+        print("[signal_scope] Clearing bridge flags and sending ping...")
+        bridge.clear_flags()
+        bridge.ping()
+        print("[signal_scope] Bridge ready")
+        status = bridge.read32(REG_STATUS)
+        print(f"[signal_scope] Status: 0x{status:08x}")
+
+        fig, ax = plt.subplots(figsize=(12, 4))
+        capture_idx = 1
+
+        while True:
+            print(f"[signal_scope] Capture cycle #{capture_idx}")
+            samples = capture_once(bridge, args)
+            plot_samples(ax, samples, args, capture_idx)
+            fig.tight_layout()
+            fig.canvas.draw_idle()
+            fig.canvas.flush_events()
+
+            if args.dump_csv:
+                write_csv(samples, Path(args.dump_csv))
+
+            if args.out:
+                out_path = Path(args.out)
+                print(f"[signal_scope] Saving plot to {out_path}...")
+                fig.savefig(out_path, dpi=150)
+                print(f"Wrote plot: {out_path}")
+
+            if not args.interactive and not args.continuous:
+                break
+
+            plt.show(block=False)
+            if args.continuous:
+                capture_idx += 1
+                continue
+            answer = input("[signal_scope] Press Enter to recapture, or 'q' + Enter to quit: ")
+            if answer.strip().lower().startswith("q"):
+                break
+            capture_idx += 1
+
+        if not args.out:
+            print("[signal_scope] Showing plot window...")
+            plt.show()
+
+    print("[signal_scope] Done")
+    return 0
+
+
+if __name__ == "__main__":
+    raise SystemExit(main())

cores/system/mcu/rtl/mcu_peripherals.v

@@ -91,11 +91,10 @@ module mcu_peripherals (
     );
 
     wb_gpio_banks #(
-        .BASE_ADDR(GPIO_BASE_ADDR),
-        .NUM_BANKS(4)
+        .num_banks(4)
     ) gpio (
-        .i_wb_clk(i_clk),
-        .i_wb_rst(i_rst),
+        .i_clk(i_clk),
+        .i_rst(i_rst),
         .i_wb_dat(gpio_wbs_dat_w),
         .i_wb_adr(gpio_wbs_adr),
         .i_wb_we(gpio_wbs_we),

cores/system/mimas_sd_adc_r2r/mimas.ucf

@@ -0,0 +1,54 @@
+# Main clock input
+NET "aclk" LOC = P126;
+NET "aclk" TNM_NET = "SYS_CLK_PIN";
+TIMESPEC TS_SYS_CLK_PIN = PERIOD "SYS_CLK_PIN" 10 ns HIGH 50 %;
+
+# Boards button row
+NET "aresetn" LOC = P120;
+NET "aresetn" IOSTANDARD = LVCMOS33;
+NET "aresetn" PULLUP;
+
+NET "adc_a" LOC = P33;
+NET "adc_a" IOSTANDARD = LVDS_33;
+NET "adc_b" LOC = P32;
+NET "adc_b" IOSTANDARD = LVDS_33;
+NET "adc_o" LOC = P34;
+NET "adc_o" IOSTANDARD = LVCMOS33;
+
+NET "r2r[0]" LOC = P131;
+NET "r2r[1]" LOC = P133;
+NET "r2r[2]" LOC = P137;
+NET "r2r[3]" LOC = P139;
+NET "r2r[4]" LOC = P141;
+NET "r2r[5]" LOC = P1;
+NET "r2r[0]" IOSTANDARD = LVCMOS33;
+NET "r2r[1]" IOSTANDARD = LVCMOS33;
+NET "r2r[2]" IOSTANDARD = LVCMOS33;
+NET "r2r[3]" IOSTANDARD = LVCMOS33;
+NET "r2r[4]" IOSTANDARD = LVCMOS33;
+NET "r2r[5]" IOSTANDARD = LVCMOS33;
+
+NET "LED[0]" LOC = P119;
+NET "LED[0]" IOSTANDARD = LVCMOS33;
+NET "LED[0]" DRIVE = 8;
+NET "LED[1]" LOC = P118;
+NET "LED[1]" IOSTANDARD = LVCMOS33;
+NET "LED[1]" DRIVE = 8;
+NET "LED[2]" LOC = P117;
+NET "LED[2]" IOSTANDARD = LVCMOS33;
+NET "LED[2]" DRIVE = 8;
+NET "LED[3]" LOC = P116;
+NET "LED[3]" IOSTANDARD = LVCMOS33;
+NET "LED[3]" DRIVE = 8;
+NET "LED[4]" LOC = P115;
+NET "LED[4]" IOSTANDARD = LVCMOS33;
+NET "LED[4]" DRIVE = 8;
+NET "LED[5]" LOC = P114;
+NET "LED[5]" IOSTANDARD = LVCMOS33;
+NET "LED[5]" DRIVE = 8;
+NET "LED[6]" LOC = P112;
+NET "LED[6]" IOSTANDARD = LVCMOS33;
+NET "LED[6]" DRIVE = 8;
+NET "LED[7]" LOC = P111;
+NET "LED[7]" IOSTANDARD = LVCMOS33;
+NET "LED[7]" DRIVE = 8;

cores/system/mimas_sd_adc_r2r/mimas_sd_adc_r2r.core

@@ -0,0 +1,47 @@
+CAPI=2:
+
+name: joppeb:system:mimas_sd_adc_r2r:1.0
+description: Mimas top-level wiring sigma-delta ADC output directly to R2R DAC
+
+filesets:
+    rtl:
+        depend:
+            - joppeb:primitive:clkgen
+            - joppeb:signal:sd_adc_q15
+            - joppeb:util:conv
+            - joppeb:signal:signal_scope_q15
+        files:
+            - rtl/toplevel.v
+        file_type: verilogSource
+
+    mimas:
+        files:
+            - mimas.ucf : {file_type : UCF}
+            - options.tcl : {file_type : tclSource}
+
+targets:
+    default:
+        filesets:
+            - rtl
+        toplevel: toplevel
+
+    mimas:
+        filesets:
+            - rtl
+            - mimas
+        toplevel: toplevel
+        parameters:
+            - FPGA_SPARTAN6=true
+        default_tool: ise
+        tools:
+            ise:
+                family: Spartan6
+                device: xc6slx9
+                package: tqg144
+                speed: -2
+
+parameters:
+    FPGA_SPARTAN6:
+        datatype: bool
+        description: Select Spartan-6 family specific implementations
+        paramtype: vlogdefine

cores/system/mimas_sd_adc_r2r/options.tcl

@@ -0,0 +1,2 @@
+project set "Create Binary Configuration File" TRUE -process "Generate Programming File"
+project set "Keep Hierarchy" Yes -process "Synthesize - XST"

cores/system/mimas_sd_adc_r2r/rtl/toplevel.v

@@ -0,0 +1,106 @@
+`timescale 1ns/1ps
+
+module toplevel(
+    input wire aclk,
+    input wire aresetn,
+
+    input wire adc_a,
+    input wire adc_b,
+    output wire adc_o,
+
+    output wire [5:0] r2r,
+    output wire [7:0] LED
+);
+    `include "conv.vh"
+
+    // Clocking
+    wire clk_100;
+    assign clk_100 = aclk;
+    wire clk_15;
+    clkgen #(
+        .CLK_IN_HZ(100000000),
+        .CLKFX_DIVIDE(20),
+        .CLKFX_MULTIPLY(3)
+    ) clk_gen_15 (
+        .clk_in(clk_100),
+        .clk_out(clk_15)
+    );
+
+    // Asynchronous assert on reset button, synchronous release in clk_15 domain.
+    localparam [17:0] RESET_RELEASE_CYCLES = 18'd150000; // ~10 ms @ 15 MHz
+    reg [17:0] rst_cnt = 18'd0;
+    reg        sys_reset_r = 1'b1;
+    always @(posedge clk_15 or negedge aresetn) begin
+        if (!aresetn) begin
+            rst_cnt <= 18'd0;
+            sys_reset_r <= 1'b1;
+        end else if (sys_reset_r) begin
+            if (rst_cnt == RESET_RELEASE_CYCLES - 1'b1)
+                sys_reset_r <= 1'b0;
+            else
+                rst_cnt <= rst_cnt + 1'b1;
+        end
+    end
+
+    wire signed [15:0] signal_q15;
+    wire signal_valid;
+    sd_adc_q15 #(
+        .R_OHM(3300),
+        .C_PF(220)
+    ) sd_adc (
+        .i_clk_15(clk_15),
+        .i_rst_n(!sys_reset_r),
+        .i_adc_a(adc_a),
+        .i_adc_b(adc_b),
+        .o_adc(adc_o),
+        .o_signal_q15(signal_q15),
+        .o_signal_valid(signal_valid)
+    );
+
+    // signal_q15 is unipolar and biased (0-3.3V -> 0..32767)
+    reg signed [15:0] signal_unbiased_q15 = 16'sd0;
+    reg signal_unbiased_valid = 1'b0;
+    localparam bias = 12050;
+    localparam gain = 2;
+    always @(posedge clk_15) begin
+        if (sys_reset_r) begin
+            signal_unbiased_q15 <= 16'sd0;
+            signal_unbiased_valid <= 1'b0;
+        end else begin
+            signal_unbiased_valid <= signal_valid;
+            if (signal_valid) begin
+                signal_unbiased_q15 <= (signal_q15 - $signed(bias)) * gain;
+            end
+        end
+    end
+
+    reg [5:0] dac_code = 6'd0;
+    always @(posedge clk_15) begin
+        if (sys_reset_r)
+            dac_code <= 6'd0;
+        else if (signal_unbiased_valid)
+            dac_code <= q15_to_uq16(signal_unbiased_q15) >> 10;
+    end
+
+    assign r2r = dac_code;
+
+    // Quick status indication: show ADC validity and most recent DAC code.
+    assign LED[0] = signal_valid;
+    assign LED[6:1] = dac_code;
+    assign LED[7] = sys_reset_r;
+
+
+    signal_scope_q15 #(
+        .depth(2**10),
+        .chain(1)
+    ) scope1 (
+        .i_clk(clk_15),
+        .i_rst(sys_reset_r),
+        .i_signal_a(signal_q15),
+        .i_signal_valid_a(signal_valid),
+        .i_signal_b(signal_unbiased_q15),
+        .i_signal_valid_b(signal_unbiased_valid),
+        .i_signal_valid_c(signal_valid),
+        .i_signal_valid_d(signal_valid)
+    );
+endmodule

cores/system/test/sw/sweep/sweep.c

@@ -35,13 +35,13 @@ void main(){
     irq_init();
 
     *LEDGR = 1;
-    *TIMER_LD = 2 * 15000000/1000;
+    *TIMER_LD = 1000 * 15000;
 
     for(;;){
-        for(int i=1000; i<10000; i+=10){
+        for(int i=500; i<6000; i+=10){
             *R_FREQ = i;
             *LEDS = i>>4;
-            // for(int j=0; j<80; j++) asm volatile("nop");
+            for(int j=0; j<800; j++) asm volatile("nop");
         }
     }
 }

cores/wb/wb_gpio_banks/rtl/wb_gpio_banks.v

@@ -13,7 +13,7 @@ module wb_gpio_banks #(
     input  wire         i_wb_we,
     input  wire         i_wb_cyc,
     input  wire         i_wb_stb,
-    output wire         o_wb_ack,
+    output reg          o_wb_ack,
 
 	input wire [num_banks*32-1:0] i_gpio,
 	output wire [num_banks*32-1:0] o_gpio
@@ -48,8 +48,8 @@ module wb_gpio_banks #(
 
 	integer bi;
 	always @* begin
-		o_wb_rdt = 0;
-		o_wb_ack = 0;
+		o_wb_rdt = 32'h00000000;
+		o_wb_ack = 1'b0;
 		for(bi=0; bi<num_banks; bi=bi+1) begin
 			if(bank_sel[bi]) begin
 				o_wb_rdt = bank_rdt[bi*32 +: 32];