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Added basic zynq setup

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Signed-off-by: Joppe Blondel <joppe@blondel.nl>
This commit is contained in:
Joppe Blondel
2022-09-03 17:11:47 +02:00
parent bf883f3355
commit cbcea361bb
10 changed files with 377 additions and 23 deletions
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1
examples/spartan6/README.md
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@ -1,5 +1,6 @@
# Spartan 6 example
Create IP files: `remotesyn -l ip total`<br>
Run full toolchain: `remotesyn -l all total`<br>
Run simulation: `remotesyn -l sim presim_total`<br>
Run post-simulation (after synthesis and implementation): `remotesyn -l sim postsim_total`<br>

64
examples/spartan6/project.cfg
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@ -1,36 +1,44 @@
# PROJECT SETTINGS
# ----------------
[server]
hostname = localhost
port = 8080
privkey = keys/id_rsa
pubkey = keys/id_rsa.pub
hostname = localhost
port = 8080
privkey = keys/id_rsa
pubkey = keys/id_rsa.pub
[project]
# Toolchain selection. choose between [ISE, VIVADO]
toolchain = ISE
out_dir = OUT
toolchain = ISE
out_dir = OUT
[target]
family = spartan6
device = xc6slx9
package = tqg144
speedgrade = -2
family = spartan6
device = xc6slx9
package = tqg144
speedgrade = -2
# HARDWARE TARGETS
# ----------------
[total]
src_vhdl = RTL/toplevel.vhd
src_verilog =
src_sysverilog =
src_constraints = CON/toplevel.ucf
src_ip =
toplevel = toplevel
extra_options = xst -glob_opt max_delay -opt_mode speed
netgen -ism
map -ol high -xe n
par -ol high -xe n
trce -v 3 -s 2 -n 3 -fastpaths
src_vhdl = RTL/toplevel.vhd
src_verilog =
src_sysverilog =
src_constraints = CON/toplevel.ucf
src_ip = blk_mem
toplevel = toplevel
extra_options = xst -glob_opt max_delay -opt_mode speed
netgen -ism
map -ol high -xe n
par -ol high -xe n
trce -v 3 -s 2 -n 3 -fastpaths
# Currently supported for ISE
# - xst -> settings added to the xst command
# - netgen -> settings added to the netgen command
# - ngd -> settings added to the ngd command
# - map -> settigs added to the map command
# - par -> settings added to the par command
# - bitgen -> settings added to the bitgen command
# - trce -> settings added to the trce command
# SIMULATION TARGETS
# ------------------
@ -53,6 +61,18 @@ src_ip =
src_sdf = OUT/total/total.map.sdf
toplevel = tb_toplevel
runtime = all
# Delay type: [min typ max]
delay = max
sdfroot = /tb_toplevel/c_toplevel
levels = 10
levels = 10
# IP BLOCKS
# ---------
[ip_blk_mem]
ip_blk_mem = xilinx.com:ip:blk_mem_gen:7.3
component_name = blk_mem
interface_type = Native
port_a_clock = 100
read_width_a = 32
write_width_a = 32
write_depth_a = 256

2
examples/zynq7000/.gitignore vendored Normal file
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OUT
.build

4
examples/zynq7000/CON/iopins.xdc Normal file
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set_property IOSTANDARD LVCMOS33 [get_ports {LED[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[0]}]
set_property PACKAGE_PIN W13 [get_ports {LED[0]}]
set_property PACKAGE_PIN W14 [get_ports {LED[1]}]

6
examples/zynq7000/README.md Normal file
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# ZYNQ 7000 example
Create IP files: `remotesyn -l ip total`<br>
Run full toolchain: `remotesyn -l all total`<br>
Run simulation (first one should create IP files for the sim targets): `remotesyn -l sim presim_total`<br>
Run post-simulation (after synthesis and implementation): `remotesyn -l sim postsim_total`<br>

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examples/zynq7000/RTL/heartbeat.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity heartbeat is
generic (
Fin : integer := 100000000;
Fout : integer := 8
);
port (
ACLK : in std_logic;
ARESETN : in std_logic;
LED : out std_logic_vector(1 downto 0)
);
end entity;
architecture structural of heartbeat is
signal iLED : std_logic_vector(1 downto 0);
begin
LED <= iLED;
process (ACLK, ARESETN)
variable cnt : integer range 0 to Fin/(2 * Fout) - 1 := 0;
begin
if ARESETN = '0' then
cnt := 0;
iLED <= "01";
elsif rising_edge(ACLK) then
if (cnt = Fin/(2 * Fout) - 1) then
cnt := 0;
iLED <= not iLED;
else
cnt := cnt + 1;
end if;
end if;
end process;
end architecture;

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examples/zynq7000/RTL/toplevel.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity toplevel is
port (
-- DDR
DDR_Addr : inout std_logic_vector(14 downto 0);
DDR_BankAddr : inout std_logic_vector(2 downto 0);
DDR_CAS_n : inout std_logic;
DDR_Clk_n : inout std_logic;
DDR_Clk : inout std_logic;
DDR_CKE : inout std_logic;
DDR_CS_n : inout std_logic;
DDR_DM : inout std_logic_vector(3 downto 0);
DDR_DQ : inout std_logic_vector(31 downto 0);
DDR_DQS_n : inout std_logic_vector(3 downto 0);
DDR_DQS_p : inout std_logic_vector(3 downto 0);
DDR_ODT : inout std_logic;
DDR_RAS_n : inout std_logic;
DDR_DSTRB : inout std_logic;
DDR_WEB : inout std_logic;
DDR_VRN : inout std_logic;
DDR_VRP : inout std_logic;
-- FIXED IO
MIO : inout std_logic_vector(53 downto 0);
ps_clk : inout std_logic;
ps_porb : inout std_logic;
ps_srstb : inout std_logic;
-- OWN DEFINED
LED : out std_logic_vector(1 downto 0)
);
end entity;
architecture structural of toplevel is
-- ----------
-- COMPONENTS
-- ----------
component zynq_ps
port (
FCLK_CLK0 : out std_logic;
FCLK_RESET0_N : out std_logic;
MIO : inout std_logic_vector(53 downto 0);
DDR_CAS_n : inout std_logic;
DDR_CKE : inout std_logic;
DDR_Clk_n : inout std_logic;
DDR_Clk : inout std_logic;
DDR_CS_n : inout std_logic;
DDR_DRSTB : inout std_logic;
DDR_ODT : inout std_logic;
DDR_RAS_n : inout std_logic;
DDR_WEB : inout std_logic;
DDR_BankAddr : inout std_logic_vector(2 downto 0);
DDR_Addr : inout std_logic_vector(14 downto 0);
DDR_VRN : inout std_logic;
DDR_VRP : inout std_logic;
DDR_DM : inout std_logic_vector(3 downto 0);
DDR_DQ : inout std_logic_vector(31 downto 0);
DDR_DQS_n : inout std_logic_vector(3 downto 0);
DDR_DQS : inout std_logic_vector(3 downto 0);
PS_SRSTB : inout std_logic;
PS_CLK : inout std_logic;
PS_PORB : inout std_logic
);
end component;
component rst_gen
port (
slowest_sync_clk : in std_logic;
ext_reset_in : in std_logic;
aux_reset_in : in std_logic;
mb_debug_sys_rst : in std_logic;
dcm_locked : in std_logic;
mb_reset : out std_logic;
bus_struct_reset : out std_logic_vector(0 downto 0);
peripheral_reset : out std_logic_vector(0 downto 0);
interconnect_aresetn : out std_logic_vector(0 downto 0);
peripheral_aresetn : out std_logic_vector(0 downto 0)
);
end component;
component heartbeat is
generic (
Fin : integer := 100000000;
Fout : integer := 8
);
port (
ACLK : in std_logic;
ARESETN : in std_logic;
LED : out std_logic_vector(1 downto 0)
);
end component;
-- -------
-- SIGNALS
-- -------
signal FCLK_CLK0 : std_logic;
signal FCLK_RESET0_N : std_logic;
signal ARESETN : std_logic_vector(0 downto 0);
begin
heartbeat_i : component heartbeat generic map(
100000000,
10
) port map(
ACLK => FCLK_CLK0,
ARESETN => ARESETN(0),
LED => LED
);
zynq_ps_i : component zynq_ps port map(
-- MIO
MIO => MIO,
-- CLOCKS
FCLK_CLK0 => FCLK_CLK0,
FCLK_RESET0_N => FCLK_RESET0_N,
-- DDR
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_Clk_n => DDR_Clk_n,
DDR_Clk => DDR_Clk,
DDR_CS_n => DDR_CS_n,
DDR_DRSTB => DDR_DSTRB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_WEB => DDR_WEB,
DDR_BankAddr => DDR_BankAddr,
DDR_Addr => DDR_Addr,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
DDR_DM => DDR_DM,
DDR_DQ => DDR_DQ,
DDR_DQS_n => DDR_DQS_n,
DDR_DQS => DDR_DQS_p,
-- PS FIXED IO
PS_SRSTB => PS_SRSTB,
PS_CLK => PS_CLK,
PS_PORB => PS_PORB
);
rst_gen_i : rst_gen port map(
slowest_sync_clk => FCLK_CLK0,
ext_reset_in => FCLK_RESET0_N,
aux_reset_in => '1',
mb_debug_sys_rst => '0',
dcm_locked => '1',
--mb_reset => mb_reset,
--bus_struct_reset => bus_struct_reset,
--peripheral_reset => peripheral_reset,
--interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => ARESETN
);
end architecture;

36
examples/zynq7000/SIM/tb_top.sv Normal file
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`timescale 1ns / 1ps
module tb_top ();
reg ACLK ;
reg ARESETN;
initial begin
ACLK = 1'b0;
end
always #5 ACLK = !ACLK;
initial begin
ARESETN = 1'b0;
tb_top.ps.inst.fpga_soft_reset(32'h1);
repeat(20)@(posedge ACLK);
ARESETN = 1'b1;
tb_top.ps.inst.fpga_soft_reset(32'h0);
repeat(5)@(posedge ACLK);
repeat(100)@(posedge ACLK);
// Write some data
//tb_top.ps.inst.write_data(32'h40000000, 4, 32'hdeadbeef, resp);
//tb_top.ps.inst.write_data(32'h40000004, 16, 128'habcdef0185274123deadbeef95123578, resp);
$display("End of simulation");
$stop;
end
zynq_ps ps (
.PS_CLK (ACLK ),
.PS_SRSTB (ARESETN ),
.PS_PORB (ARESETN )
);
endmodule

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examples/zynq7000/project.cfg Normal file
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@ -0,0 +1,85 @@
# PROJECT SETTINGS
# ----------------
[server]
hostname = localhost
port = 8080
privkey = keys/id_rsa
pubkey = keys/id_rsa.pub
[project]
# Toolchain selection. choose between [ISE, VIVADO]
toolchain = VIVADO
out_dir = OUT
[target]
family = zynq
device = xc7z010
package = clg400
speedgrade = -2
# HARDWARE TARGETS
# ----------------
[total]
src_vhdl = RTL/heartbeat.vhd
RTL/toplevel.vhd
src_verilog =
src_sysverilog =
src_constraints = CON/iopins.xdc
src_ip = zynq_ps rst_gen
toplevel = toplevel
extra_options = syn -flatten_hierarchy none -keep_equivalent_registers
netlist_top toplevel
# Currently supported for VIVADO
# - syn -> settings added to the synth_design command
# - netlist_top -> module used as toplevel for netlist/SDF generation
# defaults to the toplevel setting
# SIMULATION TARGETS
# ------------------
[presim_total]
simtype = presim
src_vhdl = RTL/heartbeat.vhd
RTL/toplevel.vhd
src_verilog =
src_sysverilog = SIM/tb_top.sv
src_ip = zynq_ps rst_gen
src_c =
toplevel = tb_top
runtime = all
[postsim_total]
simtype = postsim
src_vhdl =
src_verilog = OUT/total/impl_netlist.v
src_sysverilog = SIM/tb_top.sv
src_ip =
src_c =
src_sdf = OUT/total/impl_netlist.sdf
toplevel = tb_top
runtime = all
# Delay type: [min typ max]
delay = max
sdfroot = duv
# IP BLOCKS
# ---------
[ip_zynq_ps]
ip_zynq_ps = ip:xilinx.com:processing_system7
PCW_UIPARAM_DDR_BUS_WIDTH = 16 Bit
PCW_UIPARAM_DDR_PARTNO = MT41K256M16 RE-125
PCW_UART1_PERIPHERAL_ENABLE = 1
PCW_UART1_UART1_IO = MIO 44 .. 45
PCW_FPGA0_PERIPHERAL_FREQMHZ = 100
PCW_USE_S_AXI_GP0 = 0
PCW_USE_S_AXI_GP1 = 0
PCW_USE_M_AXI_GP0 = 0
PCW_USE_M_AXI_GP1 = 0
PCW_USE_S_AXI_HP0 = 0
PCW_USE_S_AXI_HP1 = 0
PCW_USE_S_AXI_HP2 = 0
PCW_USE_S_AXI_HP3 = 0
[ip_rst_gen]
ip_rst_gen = ip:xilinx.com:proc_sys_reset
C_EXT_RESET_HIGH = 0
C_AUX_RESET_HIGH = 0

2
remotesyn/exec_VIVADO.py
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@ -296,7 +296,7 @@ class exec_VIVADO:
f.write(f'import_files -norecurse {self.curdir}/{s}\n')
src = self.config.get(target, 'src_ip', fallback='').split()
for s in src:
f.write(f'add_files -norecurse {self.curdir}/{self.outdir}/{s}/{s}.xci\n')
f.write(f'add_files -norecurse {self.curdir}/{self.outdir}/{target}/{s}/{s}.xci\n')
src = self.config.get(target, 'src_c', fallback='').split()
for s in src:
if s.endswith('.h'):