78 lines
2.1 KiB
INI
78 lines
2.1 KiB
INI
# PROJECT SETTINGS
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# ----------------
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[server]
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hostname = localhost
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port = 8080
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privkey = keys/id_rsa
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pubkey = keys/id_rsa.pub
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[project]
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# Toolchain selection. choose between [ISE, VIVADO]
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toolchain = ISE
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out_dir = OUT
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[target]
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family = spartan6
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device = xc6slx9
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package = tqg144
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speedgrade = -2
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# HARDWARE TARGETS
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# ----------------
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[total]
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src_vhdl = RTL/toplevel.vhd
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src_verilog =
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src_sysverilog =
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src_constraints = CON/toplevel.ucf
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src_ip = blk_mem
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toplevel = toplevel
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extra_options = xst -glob_opt max_delay -opt_mode speed
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netgen -ism
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map -ol high -xe n
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par -ol high -xe n
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trce -v 3 -s 2 -n 3 -fastpaths
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# Currently supported for ISE
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# - xst -> settings added to the xst command
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# - netgen -> settings added to the netgen command
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# - ngd -> settings added to the ngd command
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# - map -> settigs added to the map command
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# - par -> settings added to the par command
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# - bitgen -> settings added to the bitgen command
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# - trce -> settings added to the trce command
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# SIMULATION TARGETS
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# ------------------
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[presim_total]
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simtype = presim
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src_vhdl = RTL/toplevel.vhd
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SIM/tb_toplevel.vhd
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src_verilog =
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src_sysverilog =
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toplevel = tb_toplevel
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runtime = all
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levels = 10
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[postsim_total]
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simtype = postsim
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src_vhdl = SIM/tb_toplevel.vhd
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src_verilog = OUT/total/total.map.v
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src_sysverilog =
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src_ip =
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src_sdf = OUT/total/total.map.sdf
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toplevel = tb_toplevel
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runtime = all
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# Delay type: [min typ max]
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delay = max
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sdfroot = /tb_toplevel/c_toplevel
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levels = 10
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# IP BLOCKS
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# ---------
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[ip_blk_mem]
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ip_blk_mem = xilinx.com:ip:blk_mem_gen:7.3
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component_name = blk_mem
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interface_type = Native
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port_a_clock = 100
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read_width_a = 32
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write_width_a = 32
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write_depth_a = 256 |