# PROJECT SETTINGS
# ----------------
[server]
hostname            = localhost
port                = 8080
privkey             = keys/id_rsa
pubkey              = keys/id_rsa.pub

[project]
# Toolchain selection. choose between [ISE, VIVADO]
toolchain           = ISE
out_dir             = OUT

[target]
family              = spartan6
device              = xc6slx9
package             = tqg144
speedgrade          = -2

# HARDWARE TARGETS
# ----------------
[total]
src_vhdl            = RTL/toplevel.vhd
src_verilog         = 
src_sysverilog      = 
src_constraints     = CON/toplevel.ucf
src_ip              = blk_mem
toplevel            = toplevel
extra_options       = xst -glob_opt max_delay -opt_mode speed
                      netgen -ism
                      map -ol high -xe n
                      par -ol high -xe n
                      trce -v 3 -s 2 -n 3 -fastpaths
# Currently supported for ISE
# - xst -> settings added to the xst command
# - netgen -> settings added to the netgen command
# - ngd -> settings added to the ngd command
# - map -> settigs added to the map command
# - par -> settings added to the par command
# - bitgen -> settings added to the bitgen command
# - trce -> settings added to the trce command

# SIMULATION TARGETS
# ------------------
[presim_total]
simtype             = presim
src_vhdl            = RTL/toplevel.vhd
                      SIM/tb_toplevel.vhd
src_verilog         = 
src_sysverilog      =
toplevel            = tb_toplevel
runtime             = all
levels              = 10

[postsim_total]
simtype             = postsim
src_vhdl            = SIM/tb_toplevel.vhd
src_verilog         = OUT/total/total.map.v
src_sysverilog      =
src_ip              = 
src_sdf             = OUT/total/total.map.sdf
toplevel            = tb_toplevel
runtime             = all
# Delay type: [min typ max]
delay               = max
sdfroot             = /tb_toplevel/c_toplevel
levels              = 10

# IP BLOCKS 
# ---------
[ip_blk_mem]
ip_blk_mem          = xilinx.com:ip:blk_mem_gen:7.3
component_name      = blk_mem
interface_type      = Native
port_a_clock        = 100
read_width_a        = 32
write_width_a       = 32
write_depth_a       = 256