85 lines
2.4 KiB
INI
85 lines
2.4 KiB
INI
# PROJECT SETTINGS
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# ----------------
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[server]
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hostname = localhost
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port = 8080
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privkey = keys/id_rsa
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pubkey = keys/id_rsa.pub
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[project]
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# Toolchain selection. choose between [ISE, VIVADO]
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toolchain = VIVADO
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out_dir = OUT
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[target]
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family = zynq
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device = xc7z010
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package = clg400
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speedgrade = -2
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# HARDWARE TARGETS
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# ----------------
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[total]
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src_vhdl = RTL/heartbeat.vhd
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RTL/toplevel.vhd
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src_verilog =
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src_sysverilog =
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src_constraints = CON/iopins.xdc
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src_ip = zynq_ps rst_gen
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toplevel = toplevel
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extra_options = syn -flatten_hierarchy none -keep_equivalent_registers
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netlist_top toplevel
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# Currently supported for VIVADO
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# - syn -> settings added to the synth_design command
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# - netlist_top -> module used as toplevel for netlist/SDF generation
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# defaults to the toplevel setting
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# SIMULATION TARGETS
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# ------------------
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[presim_total]
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simtype = presim
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src_vhdl = RTL/heartbeat.vhd
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RTL/toplevel.vhd
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src_verilog =
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src_sysverilog = SIM/tb_top.sv
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src_ip = zynq_ps rst_gen
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src_c =
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toplevel = tb_top
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runtime = all
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[postsim_total]
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simtype = postsim
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src_vhdl =
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src_verilog = OUT/total/impl_netlist.v
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src_sysverilog = SIM/tb_top.sv
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src_ip =
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src_c =
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src_sdf = OUT/total/impl_netlist.sdf
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toplevel = tb_top
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runtime = all
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# Delay type: [min typ max]
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delay = max
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sdfroot = duv
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# IP BLOCKS
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# ---------
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[ip_zynq_ps]
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ip_zynq_ps = ip:xilinx.com:processing_system7
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PCW_UIPARAM_DDR_BUS_WIDTH = 16 Bit
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PCW_UIPARAM_DDR_PARTNO = MT41K256M16 RE-125
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PCW_UART1_PERIPHERAL_ENABLE = 1
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PCW_UART1_UART1_IO = MIO 44 .. 45
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PCW_FPGA0_PERIPHERAL_FREQMHZ = 100
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PCW_USE_S_AXI_GP0 = 0
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PCW_USE_S_AXI_GP1 = 0
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PCW_USE_M_AXI_GP0 = 0
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PCW_USE_M_AXI_GP1 = 0
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PCW_USE_S_AXI_HP0 = 0
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PCW_USE_S_AXI_HP1 = 0
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PCW_USE_S_AXI_HP2 = 0
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PCW_USE_S_AXI_HP3 = 0
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[ip_rst_gen]
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ip_rst_gen = ip:xilinx.com:proc_sys_reset
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C_EXT_RESET_HIGH = 0
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C_AUX_RESET_HIGH = 0 |