# PROJECT SETTINGS
# ----------------
[server]
hostname            = localhost
port                = 8080
privkey             = keys/id_rsa
pubkey              = keys/id_rsa.pub

[project]
# Toolchain selection. choose between [ISE, VIVADO]
toolchain           = VIVADO
out_dir             = OUT

[target]
family              = zynq
device              = xc7z010
package             = clg400
speedgrade          = -2

# HARDWARE TARGETS
# ----------------
[total]
src_vhdl            = RTL/heartbeat.vhd
                      RTL/toplevel.vhd
src_verilog         =
src_sysverilog      = 
src_constraints     = CON/iopins.xdc
src_ip              = zynq_ps rst_gen
toplevel            = toplevel
extra_options       = syn -flatten_hierarchy none -keep_equivalent_registers
                      netlist_top toplevel
# Currently supported for VIVADO
# - syn -> settings added to the synth_design command
# - netlist_top -> module used as toplevel for netlist/SDF generation
#       defaults to the toplevel setting

# SIMULATION TARGETS
# ------------------
[presim_total]
simtype             = presim
src_vhdl            = RTL/heartbeat.vhd
                      RTL/toplevel.vhd
src_verilog         = 
src_sysverilog      = SIM/tb_top.sv
src_ip              = zynq_ps rst_gen
src_c               = 
toplevel            = tb_top
runtime             = all

[postsim_total]
simtype             = postsim
src_vhdl            = 
src_verilog         = OUT/total/impl_netlist.v
src_sysverilog      = SIM/tb_top.sv
src_ip              = 
src_c               = 
src_sdf             = OUT/total/impl_netlist.sdf
toplevel            = tb_top
runtime             = all
# Delay type: [min typ max]
delay               = max
sdfroot             = duv

# IP BLOCKS 
# ---------
[ip_zynq_ps]
ip_zynq_ps                      = ip:xilinx.com:processing_system7
PCW_UIPARAM_DDR_BUS_WIDTH       = 16 Bit
PCW_UIPARAM_DDR_PARTNO          = MT41K256M16 RE-125
PCW_UART1_PERIPHERAL_ENABLE     = 1
PCW_UART1_UART1_IO              = MIO 44 .. 45
PCW_FPGA0_PERIPHERAL_FREQMHZ    = 100
PCW_USE_S_AXI_GP0               = 0
PCW_USE_S_AXI_GP1               = 0
PCW_USE_M_AXI_GP0               = 0
PCW_USE_M_AXI_GP1               = 0
PCW_USE_S_AXI_HP0               = 0
PCW_USE_S_AXI_HP1               = 0
PCW_USE_S_AXI_HP2               = 0
PCW_USE_S_AXI_HP3               = 0

[ip_rst_gen]
ip_rst_gen                      = ip:xilinx.com:proc_sys_reset
C_EXT_RESET_HIGH                = 0
C_AUX_RESET_HIGH                = 0