36 lines
722 B
Systemverilog
36 lines
722 B
Systemverilog
`timescale 1ns / 1ps
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module tb_top ();
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reg ACLK ;
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reg ARESETN;
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initial begin
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ACLK = 1'b0;
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end
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always #5 ACLK = !ACLK;
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initial begin
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ARESETN = 1'b0;
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tb_top.ps.inst.fpga_soft_reset(32'h1);
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repeat(20)@(posedge ACLK);
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ARESETN = 1'b1;
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tb_top.ps.inst.fpga_soft_reset(32'h0);
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repeat(5)@(posedge ACLK);
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repeat(100)@(posedge ACLK);
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// Write some data
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//tb_top.ps.inst.write_data(32'h40000000, 4, 32'hdeadbeef, resp);
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//tb_top.ps.inst.write_data(32'h40000004, 16, 128'habcdef0185274123deadbeef95123578, resp);
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$display("End of simulation");
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$stop;
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end
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zynq_ps ps (
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.PS_CLK (ACLK ),
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.PS_SRSTB (ARESETN ),
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.PS_PORB (ARESETN )
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);
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endmodule |