39 lines
882 B
VHDL
39 lines
882 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity heartbeat is
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generic (
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Fin : integer := 100000000;
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Fout : integer := 8
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);
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port (
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ACLK : in std_logic;
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ARESETN : in std_logic;
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LED : out std_logic_vector(1 downto 0)
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);
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end entity;
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architecture structural of heartbeat is
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signal iLED : std_logic_vector(1 downto 0);
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begin
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LED <= iLED;
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process (ACLK, ARESETN)
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variable cnt : integer range 0 to Fin/(2 * Fout) - 1 := 0;
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begin
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if ARESETN = '0' then
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cnt := 0;
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iLED <= "01";
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elsif rising_edge(ACLK) then
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if (cnt = Fin/(2 * Fout) - 1) then
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cnt := 0;
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iLED <= not iLED;
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else
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cnt := cnt + 1;
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end if;
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end if;
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end process;
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end architecture; |