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base: joppe:jtagram
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joppe:master joppe:new_structure joppe:jtagram joppe:remotesyn
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compare: joppe:13f72e698f4d56e1466ca5a0c775b1e8db6a1639
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joppe:new_structure joppe:master joppe:jtagram joppe:remotesyn

3 Commits
jtagram ... 13f72e698f

Author SHA1 Message Date
Joppe Blondel
13f72e698f jtag memory interface working 2026-02-25 16:14:37 +01:00
Joppe Blondel
9930ce4461 Working CPP way of writing data 2026-02-24 16:40:17 +01:00
Joppe Blondel
8f4e887b9d Added JTAG interface with testbench 2026-02-23 15:37:49 +01:00
26 changed files with 1672 additions and 498 deletions
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4
.gitignore vendored
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@@ -1,3 +1,5 @@
out
build
env
env
__pycache*
_impactbatch.log

27
boards/mimas_v1/constraints.ucf
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@@ -24,4 +24,29 @@ NET "r2r[1]" IOSTANDARD = LVCMOS33;
NET "r2r[2]" IOSTANDARD = LVCMOS33;
NET "r2r[3]" IOSTANDARD = LVCMOS33;
NET "r2r[4]" IOSTANDARD = LVCMOS33;
NET "r2r[5]" IOSTANDARD = LVCMOS33;
NET "r2r[5]" IOSTANDARD = LVCMOS33;
NET "LED[0]" LOC = P119;
NET "LED[0]" IOSTANDARD = LVCMOS33;
NET "LED[0]" DRIVE = 8;
NET "LED[1]" LOC = P118;
NET "LED[1]" IOSTANDARD = LVCMOS33;
NET "LED[1]" DRIVE = 8;
NET "LED[2]" LOC = P117;
NET "LED[2]" IOSTANDARD = LVCMOS33;
NET "LED[2]" DRIVE = 8;
NET "LED[3]" LOC = P116;
NET "LED[3]" IOSTANDARD = LVCMOS33;
NET "LED[3]" DRIVE = 8;
NET "LED[4]" LOC = P115;
NET "LED[4]" IOSTANDARD = LVCMOS33;
NET "LED[4]" DRIVE = 8;
NET "LED[5]" LOC = P114;
NET "LED[5]" IOSTANDARD = LVCMOS33;
NET "LED[5]" DRIVE = 8;
NET "LED[6]" LOC = P112;
NET "LED[6]" IOSTANDARD = LVCMOS33;
NET "LED[6]" DRIVE = 8;
NET "LED[7]" LOC = P111;
NET "LED[7]" IOSTANDARD = LVCMOS33;
NET "LED[7]" DRIVE = 8;

61
project.cfg
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@@ -4,6 +4,15 @@ version = 0.1
out_dir = out
build_dir = build
[target.ip]
toolchain = ISE_IP
ise_settings = /opt/Xilinx/14.7/ISE_DS/settings64.sh
family = spartan6
device = xc6slx9
package = tqg144
speedgrade = -2
files_def = boards/mimas_v1/ip/clk_gen.xco
[target.synth]
toolchain = ISE
ise_settings = /opt/Xilinx/14.7/ISE_DS/settings64.sh
@@ -48,39 +57,49 @@ files_verilog = rtl/util/conv.vh
rtl/serv/servile.v
rtl/serv/serving_ram.v
rtl/serv/serving.v
rtl/arch/spartan-6/jtag_if.v
rtl/wb/wb_gpio.v
rtl/wb/wb_gpio_banks.v
rtl/core/soclet.v
rtl/wb/jtag_wb_bridge.v
rtl/core/mcu.v
files_con = boards/mimas_v1/constraints.ucf
files_other = rtl/util/rc_alpha_q15.vh
rtl/util/clog2.vh
sw/blinky/blinky.hex
[target.ip]
toolchain = ISE_IP
[target.jtag]
toolchain = ISE
ise_settings = /opt/Xilinx/14.7/ISE_DS/settings64.sh
family = spartan6
device = xc6slx9
package = tqg144
speedgrade = -2
files_def = boards/mimas_v1/ip/clk_gen.xco
toplevel = top_jtag
xst_opts = -vlgincdir rtl/util -keep_hierarchy yes
files_other =
files_con = boards/mimas_v1/constraints.ucf
files_verilog = rtl/arch/spartan-6/jtag_if.v
rtl/arch/spartan-6/clk_gen.v
rtl/wb/jtag_wb_bridge.v
rtl/wb/wb_gpio.v
rtl/toplevel/top_jtag.v
[target.sim]
[target.svftest]
toolchain = iverilog
runtime = all
toplevel = tb_sigmadelta
ivl_opts = -Irtl/util
files_verilog = sim/tb/tb_nco_q15.v
sim/tb/tb_sigmadelta.v
sim/tb/tb_mul_const.v
rtl/core/nco_q15.v
rtl/core/lvds_comparator.v
rtl/core/sigmadelta_rcmodel_q15.v
rtl/core/sigmadelta_input_q15.v
rtl/core/mul_const.v
rtl/core/lpf_iir_q15_k.v
rtl/core/decimate_by_r_q15.v
sim/overrides/sigmadelta_sampler.v
sim/overrides/clk_gen.v
files_other = rtl/util/conv.vh
rtl/util/rc_alpha_q15.vh
toplevel = tb_svf
files_verilog = sim/tb/tb_svf.v
sim/overrides/jtag_if.v
rtl/core/cdc_strobed.v
files_other = sim/other/test.svf
[target.tools]
toolchain = make
output_files = tools/test
buildroot = tools
files_makefile = tools/Makefile
files_other = tools/digilent_jtag.cpp
tools/digilent_jtag.hpp
tools/argparse.cpp
tools/argparse.hpp
tools/test.cpp

35
rtl/arch/spartan-6/jtag_if.v Normal file
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@@ -0,0 +1,35 @@
`timescale 1ns/1ps
// =============================================================================
// JTAG interface
// Spartan-6 BSCAN primitive wrapper (USER1 chain).
// =============================================================================
module jtag_if #(
parameter chain = 1
)(
input wire i_tdo,
output wire o_tck,
output wire o_tdi,
output wire o_drck,
output wire o_capture,
output wire o_shift,
output wire o_update,
output wire o_runtest,
output wire o_reset,
output wire o_sel
);
BSCAN_SPARTAN6 #(
.JTAG_CHAIN(chain)
) bscan_i (
.CAPTURE(o_capture),
.DRCK(o_drck),
.RESET(o_reset),
.RUNTEST(o_runtest),
.SEL(o_sel),
.SHIFT(o_shift),
.TCK(o_tck),
.TDI(o_tdi),
.TDO(i_tdo),
.UPDATE(o_update)
);
endmodule

49
rtl/arch/spartan-6/jtag_tap_spartan6.v
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@@ -1,49 +0,0 @@
`default_nettype none
// Spartan-6 JTAG TAP wrapper with an architecture-neutral interface.
// Re-implement this module for other FPGA families with the same port list.
module jtag_tap_spartan6
#(parameter USER_CHAIN = 1)
(
output wire o_drck,
output wire o_capture,
output wire o_shift,
output wire o_update,
output wire o_reset,
output wire o_sel,
output wire o_tdi,
input wire i_tdo
);
wire drck1;
wire drck2;
wire sel1;
wire sel2;
wire tdo1;
wire tdo2;
localparam USE_CHAIN2 = (USER_CHAIN == 2);
assign o_drck = USE_CHAIN2 ? drck2 : drck1;
assign o_sel = USE_CHAIN2 ? sel2 : sel1;
assign tdo1 = USE_CHAIN2 ? 1'b0 : i_tdo;
assign tdo2 = USE_CHAIN2 ? i_tdo : 1'b0;
BSCAN_SPARTAN6
#(.JTAG_CHAIN(USER_CHAIN))
bscan_spartan6
(
.CAPTURE(o_capture),
.DRCK1(drck1),
.DRCK2(drck2),
.RESET(o_reset),
.SEL1(sel1),
.SEL2(sel2),
.SHIFT(o_shift),
.TDI(o_tdi),
.UPDATE(o_update),
.TDO1(tdo1),
.TDO2(tdo2)
);
endmodule

34
rtl/core/jtag_if.v Normal file
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@@ -0,0 +1,34 @@
`timescale 1ns/1ps
// =============================================================================
// JTAG interface
// Generic stub model with inactive/tied-off outputs.
// =============================================================================
module jtag_if #(
parameter chain = 1
)(
input wire i_tdo,
output wire o_tck,
output wire o_tdi,
output wire o_drck,
output wire o_capture,
output wire o_shift,
output wire o_update,
output wire o_runtest,
output wire o_reset,
output wire o_sel
);
assign o_tck = 1'b0;
assign o_tdi = 1'b0;
assign o_drck = 1'b0;
assign o_capture = 1'b0;
assign o_shift = 1'b0;
assign o_update = 1'b0;
assign o_runtest = 1'b0;
assign o_reset = 1'b0;
assign o_sel = 1'b0;
// Keep lint tools quiet in generic builds where TDO is unused.
wire _unused_tdo;
assign _unused_tdo = i_tdo;
endmodule

272
rtl/core/mcu.v Normal file
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@@ -0,0 +1,272 @@
`timescale 1ns/1ps
`include "../util/clog2.vh"
module mcu #(
parameter memfile = "",
parameter memsize = 8192,
parameter sim = 1'b0
)(
input wire i_clk,
input wire i_rst,
input wire [31:0] i_GPI_A,
input wire [31:0] i_GPI_B,
input wire [31:0] i_GPI_C,
input wire [31:0] i_GPI_D,
output wire [31:0] o_GPO_A,
output wire [31:0] o_GPO_B,
output wire [31:0] o_GPO_C,
output wire [31:0] o_GPO_D
);
localparam WITH_CSR = 1;
localparam regs = 32+WITH_CSR*4;
localparam rf_width = 8;
wire rst;
wire rst_mem_reason;
wire timer_irq;
assign rst = i_rst | rst_mem_reason;
assign timer_irq = 1'b0;
// Busses
// CPU->memory
wire [31:0] wb_mem_adr;
wire [31:0] wb_mem_dat;
wire [3:0] wb_mem_sel;
wire wb_mem_we;
wire wb_mem_stb;
wire [31:0] wb_mem_rdt;
wire wb_mem_ack;
// CPU->peripherals
wire [31:0] wb_ext_adr;
wire [31:0] wb_ext_dat;
wire [3:0] wb_ext_sel;
wire wb_ext_we;
wire wb_ext_stb;
wire [31:0] wb_ext_rdt;
wire wb_ext_ack;
// CPU->RF
wire [6+WITH_CSR:0] rf_waddr;
wire [rf_width-1:0] rf_wdata;
wire rf_wen;
wire [6+WITH_CSR:0] rf_raddr;
wire [rf_width-1:0] rf_rdata;
wire rf_ren;
// combined RF and mem bus to actual RAM
wire [`CLOG2(memsize)-1:0] sram_waddr;
wire [rf_width-1:0] sram_wdata;
wire sram_wen;
wire [`CLOG2(memsize)-1:0] sram_raddr;
wire [rf_width-1:0] sram_rdata;
wire sram_ren;
// GPIO
wire [4*32-1:0] GPO;
wire [4*32-1:0] GPI;
assign o_GPO_A = GPO[32*1-1:32*0];
assign o_GPO_B = GPO[32*2-1:32*1];
assign o_GPO_C = GPO[32*3-1:32*2];
assign o_GPO_D = GPO[32*4-1:32*3];
assign GPI[32*1-1:32*0] = i_GPI_A;
assign GPI[32*2-1:32*1] = i_GPI_B;
assign GPI[32*3-1:32*2] = i_GPI_C;
assign GPI[32*4-1:32*3] = i_GPI_D;
// SERV core with mux splitting dbus into mem and ext and
// arbiter combining mem and ibus
// separate rst line to let other hardware keep core under reset
servile #(
.reset_pc(32'h0000_0000),
.reset_strategy("MINI"),
.rf_width(rf_width),
.sim(sim),
.with_csr(WITH_CSR),
.with_c(0),
.with_mdu(0)
) servile (
.i_clk(i_clk),
.i_rst(rst),
.i_timer_irq(timer_irq),
//Memory interface
.o_wb_mem_adr(wb_mem_adr),
.o_wb_mem_dat(wb_mem_dat),
.o_wb_mem_sel(wb_mem_sel),
.o_wb_mem_we(wb_mem_we),
.o_wb_mem_stb(wb_mem_stb),
.i_wb_mem_rdt(wb_mem_rdt),
.i_wb_mem_ack(wb_mem_ack),
//Extension interface
.o_wb_ext_adr(wb_ext_adr),
.o_wb_ext_dat(wb_ext_dat),
.o_wb_ext_sel(wb_ext_sel),
.o_wb_ext_we(wb_ext_we),
.o_wb_ext_stb(wb_ext_stb),
.i_wb_ext_rdt(wb_ext_rdt),
.i_wb_ext_ack(wb_ext_ack),
//RF IF
.o_rf_waddr(rf_waddr),
.o_rf_wdata(rf_wdata),
.o_rf_wen(rf_wen),
.o_rf_raddr(rf_raddr),
.o_rf_ren(rf_ren),
.i_rf_rdata(rf_rdata)
);
// WB arbiter combining RF and mem interfaces into 1
// Last 128 bytes are used for registers
servile_rf_mem_if #(
.depth(memsize),
.rf_regs(regs)
) rf_mem_if (
.i_clk (i_clk),
.i_rst (i_rst),
.i_waddr(rf_waddr),
.i_wdata(rf_wdata),
.i_wen(rf_wen),
.i_raddr(rf_raddr),
.o_rdata(rf_rdata),
.i_ren(rf_ren),
.o_sram_waddr(sram_waddr),
.o_sram_wdata(sram_wdata),
.o_sram_wen(sram_wen),
.o_sram_raddr(sram_raddr),
.i_sram_rdata(sram_rdata),
// .o_sram_ren(sram_ren),
.i_wb_adr(wb_mem_adr[`CLOG2(memsize)-1:2]),
.i_wb_stb(wb_mem_stb),
.i_wb_we(wb_mem_we) ,
.i_wb_sel(wb_mem_sel),
.i_wb_dat(wb_mem_dat),
.o_wb_rdt(wb_mem_rdt),
.o_wb_ack(wb_mem_ack)
);
memory #(
.memfile(memfile),
.depth(memsize),
.sim(sim)
) mem (
.i_clk(i_clk),
.i_rst(i_rst),
.i_waddr(sram_waddr),
.i_wdata(sram_wdata),
.i_wen(sram_wen),
.i_raddr(sram_raddr),
.o_rdata(sram_rdata),
.o_core_reset(rst_mem_reason)
);
wb_gpio_banks #(
.BASE_ADDR(32'h40000000),
.NUM_BANKS(4)
) gpio (
.i_wb_clk(i_clk),
.i_wb_rst(rst),
.i_wb_dat(wb_ext_dat),
.i_wb_adr(wb_ext_adr),
.i_wb_we(wb_ext_we),
.i_wb_stb(wb_ext_stb),
.i_wb_sel(wb_ext_sel),
.o_wb_rdt(wb_ext_rdt),
.o_wb_ack(wb_ext_ack),
.i_gpio(GPI),
.o_gpio(GPO)
);
endmodule
module memory #(
parameter memfile = "",
parameter depth = 256,
parameter sim = 1'b0,
localparam aw = `CLOG2(depth)
)(
input wire i_clk,
input wire i_rst,
input wire [aw-1:0] i_waddr,
input wire [7:0] i_wdata,
input wire i_wen,
input wire [aw-1:0] i_raddr,
output reg [7:0] o_rdata,
output wire o_core_reset
);
// The actual memory
reg [7:0] mem [0:depth-1];
wire [aw-1:0] mem_adr;
assign mem_adr = (i_wen==1'b1) ? i_waddr :
i_raddr;
// Second port wishbone
wire [31:0] wb_adr;
wire [31:0] wb_dat;
reg [31:0] wb_rdt;
wire [3:0] wb_sel;
wire wb_cyc;
wire wb_we;
wire wb_stb;
reg wb_ack;
reg wb_req_d;
wire cmd_reset;
// Driven by JTAG
jtag_wb_bridge #(
.chain(1),
.byte_aligned(1)
) jtag_wb (
.i_clk(i_clk),
.i_rst(i_rst),
.o_wb_adr(wb_adr),
.o_wb_dat(wb_dat),
.o_wb_sel(wb_sel),
.o_wb_we(wb_we),
.o_wb_cyc(wb_cyc),
.o_wb_stb(wb_stb),
.i_wb_rdt(wb_rdt),
.i_wb_ack(wb_ack),
.o_cmd_reset(cmd_reset)
);
assign o_core_reset = cmd_reset;
// Read/Write
always @(posedge i_clk) begin
if (i_rst) begin
wb_req_d <= 1'b0;
wb_ack <= 1'b0;
wb_rdt <= 32'h00000000;
o_rdata <= 32'h00000000;
end else begin
if (i_wen)
mem[mem_adr] <= i_wdata;
o_rdata <= mem[mem_adr];
wb_req_d <= wb_stb && wb_cyc;
wb_ack <= wb_req_d;
if (wb_we && wb_stb && wb_cyc)
mem[wb_adr[aw-1:0]] <= wb_dat[7:0];
wb_rdt <= {24'h000000, mem[wb_adr[aw-1:0]]};
end
end
// Preload memory
integer i;
initial begin
if(sim==1'b1) begin
for (i = 0; i < depth; i = i + 1)
mem[i] = 8'h00;
end
if(|memfile) begin
$display("Preloading %m from %s", memfile);
$readmemh(memfile, mem);
end
end
endmodule

54
rtl/serv/serving_ram_dp.v
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@@ -1,54 +0,0 @@
`default_nettype none
`include "../util/clog2.vh"
module serving_ram_dp
#(// Memory parameters
parameter depth = 256,
parameter aw = `CLOG2(depth),
parameter memfile = "",
parameter sim = 1'b0)
(
// CPU port (compatible with serving_ram)
input wire i_clk,
input wire [aw-1:0] i_waddr,
input wire [7:0] i_wdata,
input wire i_wen,
input wire [aw-1:0] i_raddr,
output reg [7:0] o_rdata,
// Debug/programming port
input wire i_dbg_clk,
input wire [aw-1:0] i_dbg_addr,
input wire [7:0] i_dbg_wdata,
input wire i_dbg_wen,
output wire [7:0] o_dbg_rdata
);
reg [7:0] mem [0:depth-1] /* verilator public */;
always @(posedge i_clk) begin
if (i_wen)
mem[i_waddr] <= i_wdata;
o_rdata <= mem[i_raddr];
end
always @(posedge i_dbg_clk) begin
if (i_dbg_wen)
mem[i_dbg_addr] <= i_dbg_wdata;
end
// Asynchronous debug read simplifies JTAG readback logic.
assign o_dbg_rdata = mem[i_dbg_addr];
integer i;
initial begin
if (sim == 1'b1) begin
for (i = 0; i < depth; i = i + 1)
mem[i] = 8'h00;
end
if (|memfile) begin
$display("Preloading %m from %s", memfile);
$readmemh(memfile, mem);
end
end
endmodule

65
rtl/serv/serving_ram_jtag.v
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@@ -1,65 +0,0 @@
`default_nettype none
`include "../util/clog2.vh"
// Drop-in serving RAM variant with USER JTAG programming access.
module serving_ram_jtag
#(
parameter depth = 256,
parameter aw = `CLOG2(depth),
parameter memfile = "",
parameter sim = 1'b0,
parameter USER_CHAIN = 1
)
(
input wire i_clk,
input wire [aw-1:0] i_waddr,
input wire [7:0] i_wdata,
input wire i_wen,
input wire [aw-1:0] i_raddr,
output wire [7:0] o_rdata
);
wire dbg_clk;
wire [aw-1:0] dbg_addr;
wire [7:0] dbg_wdata;
wire dbg_wen;
wire [7:0] dbg_rdata;
serving_ram_dp
#(
.depth(depth),
.aw(aw),
.memfile(memfile),
.sim(sim)
)
i_serving_ram_dp
(
.i_clk(i_clk),
.i_waddr(i_waddr),
.i_wdata(i_wdata),
.i_wen(i_wen),
.i_raddr(i_raddr),
.o_rdata(o_rdata),
.i_dbg_clk(dbg_clk),
.i_dbg_addr(dbg_addr),
.i_dbg_wdata(dbg_wdata),
.i_dbg_wen(dbg_wen),
.o_dbg_rdata(dbg_rdata)
);
serving_ram_jtag_bridge
#(
.depth(depth),
.aw(aw),
.USER_CHAIN(USER_CHAIN)
)
i_serving_ram_jtag_bridge
(
.o_ram_clk(dbg_clk),
.o_ram_addr(dbg_addr),
.o_ram_wdata(dbg_wdata),
.o_ram_wen(dbg_wen),
.i_ram_rdata(dbg_rdata)
);
endmodule

107
rtl/serv/serving_ram_jtag_bridge.v
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@@ -1,107 +0,0 @@
`default_nettype none
`include "../util/clog2.vh"
// Simple USER JTAG data-register protocol (LSB-first):
// bit[0] : write_enable (1=write, 0=read/select)
// bit[32:1] : 32-bit address
// bit[40:33] : write data
//
// On UPDATE:
// - write command: writes byte to RAM
// - read command : updates current read address for next CAPTURE/SHIFT readback
// - RAM uses the lower aw address bits from the 32-bit protocol address
//
// On CAPTURE, readback register loads:
// bit[0] : valid (always 1)
// bit[8:1] : read data at current read address
// remaining bits : zero
module serving_ram_jtag_bridge
#(
parameter depth = 256,
parameter aw = `CLOG2(depth),
parameter USER_CHAIN = 1
)
(
output wire o_ram_clk,
output wire [aw-1:0] o_ram_addr,
output wire [7:0] o_ram_wdata,
output wire o_ram_wen,
input wire [7:0] i_ram_rdata
);
localparam integer JTAG_AW = 32;
localparam integer FRAME_W = 1 + JTAG_AW + 8;
localparam integer PAD_W = FRAME_W - 9;
wire tap_drck;
wire tap_shift;
wire tap_update;
wire tap_reset;
wire tap_sel;
wire tap_tdi;
wire tap_tdo;
reg [FRAME_W-1:0] shift_in;
reg [FRAME_W-1:0] shift_out;
reg [aw-1:0] read_addr;
reg shift_active_d;
wire cmd_write;
wire [JTAG_AW-1:0] cmd_addr;
wire [aw-1:0] cmd_addr_ram;
wire [7:0] cmd_wdata;
assign cmd_write = shift_in[0];
assign cmd_addr = shift_in[JTAG_AW:1];
assign cmd_wdata = shift_in[JTAG_AW+8:JTAG_AW+1];
assign cmd_addr_ram = cmd_addr[aw-1:0];
// Update command shift register and shift response out on DRCK.
// Readback data is loaded on the first shift pulse of a DR scan.
always @(posedge tap_drck or posedge tap_reset) begin
if (tap_reset) begin
shift_in <= {FRAME_W{1'b0}};
shift_out <= {FRAME_W{1'b0}};
shift_active_d <= 1'b0;
end else if (tap_sel && tap_shift) begin
if (!shift_active_d)
shift_out <= {{PAD_W{1'b0}}, i_ram_rdata, 1'b1};
else
shift_out <= {1'b0, shift_out[FRAME_W-1:1]};
shift_in <= {tap_tdi, shift_in[FRAME_W-1:1]};
shift_active_d <= 1'b1;
end else begin
shift_active_d <= 1'b0;
end
end
// Read command selects the address for the next capture.
always @(posedge tap_update or posedge tap_reset) begin
if (tap_reset)
read_addr <= {aw{1'b0}};
else if (tap_sel && !cmd_write)
read_addr <= cmd_addr_ram;
end
assign o_ram_clk = tap_update;
assign o_ram_wen = tap_update & tap_sel & cmd_write;
assign o_ram_wdata = cmd_wdata;
assign o_ram_addr = tap_update ? cmd_addr_ram : read_addr;
assign tap_tdo = shift_out[0];
jtag_tap_spartan6
#(.USER_CHAIN(USER_CHAIN))
i_jtag_tap
(
.o_drck(tap_drck),
.o_capture(),
.o_shift(tap_shift),
.o_update(tap_update),
.o_reset(tap_reset),
.o_sel(tap_sel),
.o_tdi(tap_tdi),
.i_tdo(tap_tdo)
);
endmodule

6
rtl/toplevel/top_generic.v
View File

@@ -7,11 +7,13 @@ module top_generic(
output wire led_green,
output wire led_red,
output wire[5:0] r2r
output wire[5:0] r2r,
output wire[7:0] LED
);
`include "conv.vh"
assign led_green = 1'b0;
assign led_red = 1'b0;
assign LED = 8'h00;
// Clocking
wire clk_100;
@@ -27,7 +29,7 @@ module top_generic(
wire [31:0] GPIO_C;
wire [31:0] GPIO_D;
soclet #(
mcu #(
.memfile("../sw/sweep/sweep.hex")
) mcu (
.i_clk(clk_15),

75
rtl/toplevel/top_jtag.v Normal file
View File

@@ -0,0 +1,75 @@
module top_jtag(
input wire aclk,
input wire aresetn,
output wire led_green,
output wire led_red,
output wire [7:0] LED,
output wire [5:0] r2r
);
// Clocking
wire clk_100;
wire clk_15;
assign clk_100 = aclk;
clk_gen clk(
.clk_in(clk_100),
.clk_out_15(clk_15)
);
wire i_rst;
assign i_rst = !aresetn;
wire [31:0] wb_adr;
wire [31:0] wb_dat;
wire [31:0] wb_rdt;
wire [3:0] wb_sel;
wire wb_cyc;
wire wb_we;
wire wb_stb;
wire wb_ack;
wire cmd_reset;
jtag_wb_bridge #(
.chain(1)
) jtag_wb (
.i_clk(clk_15),
.i_rst(!aresetn),
.o_wb_adr(wb_adr),
.o_wb_dat(wb_dat),
.o_wb_sel(wb_sel),
.o_wb_we(wb_we),
.o_wb_cyc(wb_cyc),
.o_wb_stb(wb_stb),
.i_wb_rdt(wb_rdt),
.i_wb_ack(wb_ack),
.o_cmd_reset(cmd_reset)
);
wire [31:0] gpio;
wire [31:0] gpio_in;
assign gpio_in = 32'h0;
wb_gpio #(
.address(32'h00000000)
) u_wb_gpio (
.i_wb_clk(clk_15),
.i_wb_rst(i_rst | cmd_reset),
.i_wb_adr(wb_adr),
.i_wb_dat(wb_dat),
.i_wb_sel(wb_sel),
.i_wb_we(wb_we),
.i_wb_stb(wb_stb & wb_cyc),
.i_gpio(gpio_in),
.o_wb_rdt(wb_rdt),
.o_wb_ack(wb_ack),
.o_gpio(gpio)
);
assign LED = gpio[7:0];
assign r2r = gpio[13:8];
assign led_green = gpio[30];
assign led_red = gpio[31];
endmodule

196
rtl/wb/jtag_wb_bridge.v Normal file
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@@ -0,0 +1,196 @@
`timescale 1ns/1ps
module jtag_wb_bridge #(
parameter integer chain = 1,
// 0: Use cmd_addr[1:0] to select byte lane on 32-bit WB data bus.
// 1: Always use lane 0 (LSB), for byte-wide memories that return data in [7:0].
parameter integer byte_aligned = 0
)(
input wire i_clk,
input wire i_rst,
output wire [31:0] o_wb_adr,
output wire [31:0] o_wb_dat,
output wire [3:0] o_wb_sel,
output wire o_wb_we,
output wire o_wb_cyc,
output wire o_wb_stb,
input wire [31:0] i_wb_rdt,
input wire i_wb_ack,
output wire o_cmd_reset
);
// JTAG interface wires
wire jtag_tck;
wire jtag_tdi;
wire jtag_drck;
wire jtag_capture;
wire jtag_shift;
wire jtag_update;
wire jtag_runtest;
wire jtag_reset;
wire jtag_sel;
reg [41:0] jtag_q;
wire [41:0] jtag_data_in;
wire jtag_async_reset;
jtag_if #(
.chain(chain)
) jtag (
.i_tdo(jtag_q[0]),
.o_tck(jtag_tck),
.o_tdi(jtag_tdi),
.o_drck(jtag_drck),
.o_capture(jtag_capture),
.o_shift(jtag_shift),
.o_update(jtag_update),
.o_runtest(jtag_runtest),
.o_reset(jtag_reset),
.o_sel(jtag_sel)
);
assign jtag_async_reset = jtag_reset || i_rst;
// JTAG shift register behavior
always @(posedge jtag_drck or posedge jtag_async_reset) begin
if (jtag_async_reset) begin
jtag_q <= 42'b0;
end else if (jtag_sel && jtag_capture) begin
jtag_q <= jtag_data_in;
end else if (jtag_sel && jtag_shift) begin
jtag_q <= {jtag_tdi, jtag_q[41:1]};
end
end
// -----------------------------------------------------------------------------
// JTAG -> i_clk crossing using toggle request/ack handshake.
// Command packet format: [41]=we, [40]=reset, [39:8]=addr, [7:0]=wdata
// -----------------------------------------------------------------------------
reg [41:0] j_cmd_hold;
reg j_req_tgl;
reg j_ack_sync_1;
reg j_ack_sync_2;
reg s_ack_tgl;
reg s_req_sync_1;
reg s_req_sync_2;
reg s_req_sync_3;
reg [41:0] s_cmd_sync_1;
reg [41:0] s_cmd_sync_2;
always @(posedge jtag_drck or posedge jtag_async_reset) begin
if (jtag_async_reset) begin
j_ack_sync_1 <= 1'b0;
j_ack_sync_2 <= 1'b0;
end else begin
j_ack_sync_1 <= s_ack_tgl;
j_ack_sync_2 <= j_ack_sync_1;
end
end
always @(posedge jtag_update or posedge jtag_async_reset) begin
if (jtag_async_reset) begin
j_cmd_hold <= 42'b0;
j_req_tgl <= 1'b0;
end else if (jtag_sel && (j_ack_sync_2 == j_req_tgl)) begin
j_cmd_hold <= jtag_q;
j_req_tgl <= ~j_req_tgl;
end
end
// -----------------------------------------------------------------------------
// Wishbone classic single-request master (1 outstanding transaction max).
// -----------------------------------------------------------------------------
reg wb_busy;
reg [31:0] wb_adr_r;
reg [31:0] wb_dat_r;
reg [3:0] wb_sel_r;
reg wb_we_r;
reg cmd_reset_pulse_r;
reg [31:0] resp_addr_r;
reg [7:0] resp_data_r;
wire req_pulse;
wire [7:0] cmd_wdata;
wire [31:0] cmd_addr;
wire cmd_reset;
wire cmd_we;
wire [1:0] req_lane;
wire [1:0] resp_lane;
assign req_pulse = s_req_sync_2 ^ s_req_sync_3;
assign cmd_wdata = s_cmd_sync_2[7:0];
assign cmd_addr = s_cmd_sync_2[39:8];
assign cmd_reset = s_cmd_sync_2[40];
assign cmd_we = s_cmd_sync_2[41];
assign req_lane = byte_aligned ? 2'b00 : cmd_addr[1:0];
assign resp_lane = byte_aligned ? 2'b00 : wb_adr_r[1:0];
assign o_wb_adr = wb_adr_r;
assign o_wb_dat = wb_dat_r;
assign o_wb_sel = wb_sel_r;
assign o_wb_we = wb_we_r;
assign o_wb_cyc = wb_busy;
assign o_wb_stb = wb_busy;
assign o_cmd_reset = cmd_reset_pulse_r;
always @(posedge i_clk) begin
if (i_rst) begin
s_ack_tgl <= 1'b0;
s_req_sync_1 <= 1'b0;
s_req_sync_2 <= 1'b0;
s_req_sync_3 <= 1'b0;
s_cmd_sync_1 <= 42'b0;
s_cmd_sync_2 <= 42'b0;
wb_busy <= 1'b0;
wb_adr_r <= 32'b0;
wb_dat_r <= 32'b0;
wb_sel_r <= 4'b0000;
wb_we_r <= 1'b0;
cmd_reset_pulse_r <= 1'b0;
resp_addr_r <= 32'b0;
resp_data_r <= 8'b0;
end else begin
s_req_sync_1 <= j_req_tgl;
s_req_sync_2 <= s_req_sync_1;
s_req_sync_3 <= s_req_sync_2;
s_cmd_sync_1 <= j_cmd_hold;
s_cmd_sync_2 <= s_cmd_sync_1;
cmd_reset_pulse_r <= 1'b0;
if (req_pulse && !wb_busy) begin
wb_busy <= 1'b1;
wb_we_r <= cmd_we;
wb_adr_r <= cmd_addr;
case (req_lane)
2'b00: begin wb_sel_r <= 4'b0001; wb_dat_r <= {24'b0, cmd_wdata}; end
2'b01: begin wb_sel_r <= 4'b0010; wb_dat_r <= {16'b0, cmd_wdata, 8'b0}; end
2'b10: begin wb_sel_r <= 4'b0100; wb_dat_r <= {8'b0, cmd_wdata, 16'b0}; end
default: begin wb_sel_r <= 4'b1000; wb_dat_r <= {cmd_wdata, 24'b0}; end
endcase
cmd_reset_pulse_r <= cmd_reset;
end
if (wb_busy && i_wb_ack) begin
wb_busy <= 1'b0;
wb_we_r <= 1'b0;
resp_addr_r <= wb_adr_r;
case (resp_lane)
2'b00: resp_data_r <= i_wb_rdt[7:0];
2'b01: resp_data_r <= i_wb_rdt[15:8];
2'b10: resp_data_r <= i_wb_rdt[23:16];
default: resp_data_r <= i_wb_rdt[31:24];
endcase
s_ack_tgl <= s_req_sync_2;
end
end
end
assign jtag_data_in = {2'b00, resp_addr_r, resp_data_r};
endmodule

196
scripts/jtag_write_ram.py
View File

@@ -1,196 +0,0 @@
#!/usr/bin/env python3
"""Write a file into serving_ram_jtag over Spartan-6 USER JTAG via OpenOCD.
This script targets the protocol implemented by rtl/serv/serving_ram_jtag_bridge.v:
frame bit[0] = write_enable
frame bit[32:1] = 32-bit address
frame bit[40:33] = data byte
Notes:
- Frame is shifted LSB-first (OpenOCD drscan integer value format matches this).
- USER1/USER2 opcode selection is Spartan-6 specific (IR opcodes 0x02/0x03, IR length 6).
"""
from __future__ import annotations
import argparse
import pathlib
import re
import subprocess
import sys
import tempfile
from typing import Dict, List, Tuple
JTAG_ADDR_W = 32
JTAG_FRAME_W = 1 + JTAG_ADDR_W + 8
def parse_args() -> argparse.Namespace:
p = argparse.ArgumentParser(description="Write file to serving RAM over JTAG")
p.add_argument("input", help="Input file (.bin or readmemh-style .hex/.mem)")
p.add_argument(
"--ram-addr-width",
"--addr-width",
dest="ram_addr_width",
type=int,
default=8,
help="RAM address width (aw) in HDL, default: 8",
)
p.add_argument("--base-addr", type=lambda x: int(x, 0), default=0, help="Base address for .bin input")
p.add_argument("--tap", default="xc6s.tap", help="OpenOCD tap name (default: xc6s.tap)")
p.add_argument(
"--user-chain",
type=int,
choices=[1, 2],
default=1,
help="BSCAN user chain used in HDL (default: 1)",
)
p.add_argument("--openocd-cfg", action="append", default=[], help="OpenOCD -f config file (repeatable)")
p.add_argument("--openocd-cmd", action="append", default=[], help="Extra OpenOCD -c command before programming")
p.add_argument("--limit", type=int, default=None, help="Write only first N bytes")
p.add_argument("--dry-run", action="store_true", help="Generate and print TCL only")
return p.parse_args()
def _strip_line_comments(line: str) -> str:
return line.split("//", 1)[0]
def parse_readmemh_text(path: pathlib.Path) -> Dict[int, int]:
"""Parse a simple readmemh-style file with optional @address directives."""
text = path.read_text(encoding="utf-8")
words: Dict[int, int] = {}
addr = 0
for raw_line in text.splitlines():
line = _strip_line_comments(raw_line).strip()
if not line:
continue
for tok in line.split():
tok = tok.strip()
if not tok:
continue
if tok.startswith("@"):
addr = int(tok[1:], 16)
continue
if not re.fullmatch(r"[0-9a-fA-F]+", tok):
raise ValueError(f"Unsupported token '{tok}' in {path}")
val = int(tok, 16)
if val < 0 or val > 0xFF:
raise ValueError(f"Byte value out of range at address 0x{addr:x}: {tok}")
words[addr] = val
addr += 1
return words
def load_image(path: pathlib.Path, base_addr: int) -> List[Tuple[int, int]]:
suffix = path.suffix.lower()
if suffix == ".bin":
blob = path.read_bytes()
return [(base_addr + i, b) for i, b in enumerate(blob)]
if suffix in {".hex", ".mem", ".vmem"}:
words = parse_readmemh_text(path)
return sorted(words.items())
raise ValueError("Unsupported input format. Use .bin, .hex, .mem, or .vmem")
def build_write_frame(addr: int, data: int) -> int:
return (data << (JTAG_ADDR_W + 1)) | ((addr & ((1 << JTAG_ADDR_W) - 1)) << 1) | 0x1
def build_openocd_tcl(entries: List[Tuple[int, int]], tap: str, user_chain: int, pre_cmds: List[str]) -> str:
ir_opcode = 0x02 if user_chain == 1 else 0x03
lines: List[str] = []
lines.append("init")
for cmd in pre_cmds:
lines.append(cmd)
lines.append(f"irscan {tap} 0x{ir_opcode:x} -endstate IDLE")
for addr, data in entries:
frame = build_write_frame(addr, data)
lines.append(f"drscan {tap} {JTAG_FRAME_W} 0x{frame:x} -endstate IDLE")
lines.append("shutdown")
lines.append("")
return "\n".join(lines)
def run_openocd(cfg_files: List[str], script_path: pathlib.Path) -> int:
cmd = ["openocd"]
for cfg in cfg_files:
cmd += ["-f", cfg]
cmd += ["-f", str(script_path)]
proc = subprocess.run(cmd)
return proc.returncode
def main() -> int:
args = parse_args()
in_path = pathlib.Path(args.input)
if not in_path.exists():
print(f"error: input file not found: {in_path}", file=sys.stderr)
return 2
entries = load_image(in_path, args.base_addr)
if args.limit is not None:
entries = entries[: args.limit]
if not entries:
print("error: no bytes found to write", file=sys.stderr)
return 2
if args.ram_addr_width < 1 or args.ram_addr_width > JTAG_ADDR_W:
print(
f"error: --ram-addr-width must be in [1, {JTAG_ADDR_W}] for this protocol",
file=sys.stderr,
)
return 2
max_jtag_addr = (1 << JTAG_ADDR_W) - 1
max_addr = (1 << args.ram_addr_width) - 1
for addr, _ in entries:
if addr < 0 or addr > max_jtag_addr:
print(
f"error: address 0x{addr:x} exceeds 32-bit protocol range (max 0x{max_jtag_addr:x})",
file=sys.stderr,
)
return 2
if addr > max_addr:
print(
f"error: address 0x{addr:x} exceeds RAM addr width {args.ram_addr_width} (max 0x{max_addr:x})",
file=sys.stderr,
)
return 2
tcl = build_openocd_tcl(entries, args.tap, args.user_chain, args.openocd_cmd)
if args.dry_run:
print(tcl, end="")
print(f"# bytes: {len(entries)}", file=sys.stderr)
return 0
if not args.openocd_cfg:
print("error: provide at least one --openocd-cfg unless using --dry-run", file=sys.stderr)
return 2
with tempfile.NamedTemporaryFile("w", suffix=".tcl", delete=False) as tf:
tf.write(tcl)
tcl_path = pathlib.Path(tf.name)
print(f"Programming {len(entries)} bytes via JTAG...")
rc = run_openocd(args.openocd_cfg, tcl_path)
if rc != 0:
print(f"error: openocd failed with exit code {rc}", file=sys.stderr)
print(f"TCL kept at: {tcl_path}", file=sys.stderr)
return rc
print("Done.")
return 0
if __name__ == "__main__":
raise SystemExit(main())

10
sim/other/test.svf Normal file
View File

@@ -0,0 +1,10 @@
TRST ABSENT;
ENDIR IDLE;
ENDDR IDLE;
STATE RESET;
STATE IDLE;
SIR 6 TDI (02);
SDR 42 TDI (3A987654321);
STATE IDLE;

196
sim/overrides/jtag_if.v Normal file
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@@ -0,0 +1,196 @@
`timescale 1ns/1ps
// =============================================================================
// JTAG interface (simulation override)
// Behavioral SVF player for simple USER-chain simulation.
//
// Supported SVF commands (line-oriented, uppercase recommended):
// - SIR <n> TDI (<hex>);
// - SDR <n> TDI (<hex>);
// - RUNTEST <n> TCK;
// - STATE RESET;
// - STATE IDLE;
// Other lines are ignored.
// =============================================================================
module jtag_if #(
parameter integer chain = 1,
parameter [8*256-1:0] SVF_FILE = "write_jtag.svf",
parameter integer TCK_HALF_PERIOD_NS = 50,
parameter [31:0] USER_IR_OPCODE = 32'h00000002
)(
input wire i_tdo,
output reg o_tck,
output reg o_tdi,
output reg o_drck,
output reg o_capture,
output reg o_shift,
output reg o_update,
output reg o_runtest,
output reg o_reset,
output reg o_sel
);
integer fd;
integer got;
integer nbits;
integer cycles;
integer i;
integer line_no;
integer scan_bits;
reg [8*1024-1:0] line;
reg [8*32-1:0] cmd;
reg [8*32-1:0] arg1;
reg [8*256-1:0] svf_file_path;
reg [4095:0] scan_data;
reg [31:0] current_ir;
reg selected;
// Keep linters quiet: TDO is not consumed by this simple player.
wire _unused_tdo;
assign _unused_tdo = i_tdo;
task pulse_tck;
begin
#TCK_HALF_PERIOD_NS o_tck = 1'b1;
#TCK_HALF_PERIOD_NS o_tck = 1'b0;
end
endtask
task pulse_drck_shift;
input bit_in;
begin
o_tdi = bit_in;
o_shift = 1'b1;
#TCK_HALF_PERIOD_NS begin
o_tck = 1'b1;
o_drck = 1'b1;
end
#TCK_HALF_PERIOD_NS begin
o_tck = 1'b0;
o_drck = 1'b0;
end
end
endtask
task pulse_capture;
begin
o_capture = 1'b1;
#TCK_HALF_PERIOD_NS begin
o_tck = 1'b1;
o_drck = 1'b1;
end
#TCK_HALF_PERIOD_NS begin
o_tck = 1'b0;
o_drck = 1'b0;
o_capture = 1'b0;
end
end
endtask
task pulse_update;
begin
o_shift = 1'b0;
#TCK_HALF_PERIOD_NS o_update = 1'b1;
#TCK_HALF_PERIOD_NS o_update = 1'b0;
end
endtask
initial begin
// Default output levels
o_tck = 1'b0;
o_tdi = 1'b0;
o_drck = 1'b0;
o_capture = 1'b0;
o_shift = 1'b0;
o_update = 1'b0;
o_runtest = 1'b0;
o_reset = 1'b0;
o_sel = 1'b0;
selected = 1'b0;
current_ir = 32'h0;
line_no = 0;
svf_file_path = SVF_FILE;
// Deterministic startup reset pulse before consuming SVF.
o_reset = 1'b1;
#TCK_HALF_PERIOD_NS o_tck = 1'b1;
#TCK_HALF_PERIOD_NS o_tck = 1'b0;
#TCK_HALF_PERIOD_NS o_tck = 1'b1;
#TCK_HALF_PERIOD_NS o_tck = 1'b0;
o_reset = 1'b0;
fd = $fopen(svf_file_path, "r");
if (fd == 0) begin
$display("jtag_if(sim): could not open SVF file '%0s'", svf_file_path);
end else begin
while (!$feof(fd)) begin
line = {8*1024{1'b0}};
got = $fgets(line, fd);
line_no = line_no + 1;
if (got > 0) begin
cmd = {8*32{1'b0}};
arg1 = {8*32{1'b0}};
scan_data = {4096{1'b0}};
nbits = 0;
cycles = 0;
got = $sscanf(line, "%s", cmd);
if (got < 1) begin
// Empty line
end else if (cmd == "!") begin
// Comment line
end else if (cmd == "SIR") begin
got = $sscanf(line, "SIR %d TDI (%h);", nbits, scan_data);
if (got == 2) begin
current_ir = scan_data[31:0];
selected = (current_ir == USER_IR_OPCODE);
o_sel = selected;
// Emit TCK pulses for IR shift activity.
scan_bits = nbits;
if (scan_bits > 4096) scan_bits = 4096;
for (i = 0; i < scan_bits; i = i + 1) begin
o_tdi = scan_data[i];
pulse_tck;
end
end
end else if (cmd == "SDR") begin
got = $sscanf(line, "SDR %d TDI (%h);", nbits, scan_data);
if (got == 2) begin
if (selected) begin
pulse_capture;
end
scan_bits = nbits;
if (scan_bits > 4096) scan_bits = 4096;
for (i = 0; i < scan_bits; i = i + 1) begin
pulse_drck_shift(scan_data[i]);
end
if (selected) begin
pulse_update;
end
end
end else if (cmd == "RUNTEST") begin
got = $sscanf(line, "RUNTEST %d TCK;", cycles);
if (got == 1) begin
o_runtest = 1'b1;
for (i = 0; i < cycles; i = i + 1)
pulse_tck;
o_runtest = 1'b0;
end
end else if (cmd == "STATE") begin
got = $sscanf(line, "STATE %s", arg1);
if (got == 1) begin
if (arg1 == "RESET;") begin
o_reset = 1'b1;
#TCK_HALF_PERIOD_NS o_reset = 1'b0;
selected = 1'b0;
o_sel = 1'b0;
end
end
end
end
end
$fclose(fd);
end
end
endmodule

106
sim/tb/tb_svf.v Normal file
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@@ -0,0 +1,106 @@
`timescale 1ns/1ps
module tb_svf();
reg clk;
reg resetn;
initial clk <= 1'b0;
initial resetn <= 1'b0;
always #33.33 clk <= !clk;
initial #40 resetn <= 1'b1;
wire [7:0] led_out;
jtag_byte_sink #(
.SVF_FILE("sim/other/test.svf"),
.TCK_HALF_PERIOD_NS(500)
) dut (
.i_clk(clk),
.i_rst(!resetn),
.o_led(led_out)
);
initial begin
$dumpfile("out.vcd");
$dumpvars;
#200_000;
$finish;
end
endmodule
module jtag_byte_sink #(
parameter [8*256-1:0] SVF_FILE = "",
parameter integer TCK_HALF_PERIOD_NS = 50
)(
input wire i_clk,
input wire i_rst,
output reg [7:0] o_led
);
initial o_led <= 0;
// JTAG interface wires
wire jtag_tck;
wire jtag_tdi;
wire jtag_drck;
wire jtag_capture;
wire jtag_shift;
wire jtag_update;
wire jtag_runtest;
wire jtag_reset;
wire jtag_sel;
reg [41:0] jtag_q;
reg [41:0] jtag_data;
wire jtag_async_reset;
jtag_if #(
.chain(1),
.SVF_FILE(SVF_FILE),
.TCK_HALF_PERIOD_NS(TCK_HALF_PERIOD_NS),
.USER_IR_OPCODE(32'h0000_0002)
) jtag (
.i_tdo(jtag_q[0]),
.o_tck(jtag_tck),
.o_tdi(jtag_tdi),
.o_drck(jtag_drck),
.o_capture(jtag_capture),
.o_shift(jtag_shift),
.o_update(jtag_update),
.o_runtest(jtag_runtest),
.o_reset(jtag_reset),
.o_sel(jtag_sel)
);
assign jtag_async_reset = jtag_reset || i_rst;
always @(posedge jtag_drck or posedge jtag_async_reset) begin
if (jtag_async_reset) begin
jtag_q <= 0;
end else if (jtag_sel && jtag_capture) begin
jtag_q <= jtag_data;
end else if (jtag_sel && jtag_shift) begin
jtag_q <= {jtag_tdi, jtag_q[41:1]};
end
end
always @(posedge jtag_update or posedge jtag_async_reset) begin
if (jtag_async_reset) begin
jtag_data <= 0;
end else if (jtag_sel) begin
jtag_data <= jtag_q;
end
end
wire [41:0] j_data;
wire j_data_update;
cdc_strobed #(42) j_data_cdc (
.i_clk_a(i_clk),
.i_clk_b(i_clk),
.i_data(jtag_data),
.i_strobe(jtag_update),
.o_data(j_data),
.o_strobe(j_data_update)
);
endmodule

2
sw/blinky/link.ld
View File

@@ -3,7 +3,7 @@ ENTRY(_start)
MEMORY
{
RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 8K
RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 8064
}
SECTIONS

2
sw/sweep/link.ld
View File

@@ -3,7 +3,7 @@ ENTRY(_start)
MEMORY
{
RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 8K
RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 8064
}
SECTIONS

2
tools/.gitignore vendored Normal file
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@@ -0,0 +1,2 @@
*.o
test

32
tools/Makefile Normal file
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@@ -0,0 +1,32 @@
TOOLCHAIN_PREFIX ?=
CC := $(TOOLCHAIN_PREFIX)g++
TARGET := test
SRCS_C :=
SRCS_CPP:= test.cpp digilent_jtag.cpp argparse.cpp
OBJS := $(SRCS_C:.c=.o) $(SRCS_CPP:.cpp=.o)
ADEPT_LIBDIR := /opt/packages/digilent.adept.runtime_2.27.9-x86_64/lib64
CFLAGS :=
ASFLAGS :=
LDFLAGS := -L$(ADEPT_LIBDIR) -Wl,--disable-new-dtags -Wl,-rpath,$(ADEPT_LIBDIR)
LIBS := -ldjtg -ldmgr -ldpcomm -ldabs -ldftd2xx
.PHONY: all clean size
all: $(TARGET)
$(TARGET): $(OBJS)
$(CC) $(LDFLAGS) -o $@ $(OBJS) $(LIBS)
%.o: %.c
$(CC) $(CFLAGS) -c -o $@ $<
%.o: %.cpp
$(CC) $(CFLAGS) -c -o $@ $<
clean:
rm -f $(TARGET) $(OBJS)

158
tools/argparse.cpp Normal file
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@@ -0,0 +1,158 @@
#include "argparse.hpp"
#include <cerrno>
#include <climits>
#include <cstdio>
#include <cstdlib>
#include <sstream>
ArgParser::ArgParser(std::string program_name)
: program_name_(std::move(program_name)) {}
void ArgParser::addString(const std::string &name,
const std::string &default_value,
const std::string &help,
bool required) {
order_.push_back(name);
meta_[name] = {OptionType::kString, help, required};
string_values_[name] = default_value;
provided_[name] = false;
}
void ArgParser::addInt(const std::string &name,
int default_value,
const std::string &help,
bool required) {
order_.push_back(name);
meta_[name] = {OptionType::kInt, help, required};
int_values_[name] = default_value;
provided_[name] = false;
}
bool ArgParser::parse(int argc, char **argv, std::string *error) {
for (int i = 1; i < argc; ++i) {
std::string token(argv[i]);
if (token == "--help" || token == "-h") {
if (error) {
*error = "help";
}
return false;
}
if (token.rfind("--", 0) != 0) {
if (error) {
*error = "Unexpected positional argument: " + token;
}
return false;
}
std::string key;
std::string value;
size_t eq = token.find('=');
if (eq == std::string::npos) {
key = token.substr(2);
if (i + 1 >= argc) {
if (error) {
*error = "Missing value for --" + key;
}
return false;
}
value = argv[++i];
} else {
key = token.substr(2, eq - 2);
value = token.substr(eq + 1);
}
auto m = meta_.find(key);
if (m == meta_.end()) {
if (error) {
*error = "Unknown option: --" + key;
}
return false;
}
if (m->second.type == OptionType::kString) {
string_values_[key] = value;
provided_[key] = true;
} else {
errno = 0;
char *endp = nullptr;
long parsed = std::strtol(value.c_str(), &endp, 0);
if (errno != 0 || endp == value.c_str() || *endp != '\0' ||
parsed < INT_MIN || parsed > INT_MAX) {
if (error) {
*error = "Invalid integer for --" + key + ": " + value;
}
return false;
}
int_values_[key] = static_cast<int>(parsed);
provided_[key] = true;
}
}
for (const auto &key : order_) {
auto m = meta_.find(key);
if (m != meta_.end() && m->second.required && !has(key)) {
if (error) {
*error = "Missing required option: --" + key;
}
return false;
}
}
return true;
}
bool ArgParser::has(const std::string &name) const {
auto p = provided_.find(name);
return p != provided_.end() && p->second;
}
std::string ArgParser::getString(const std::string &name) const {
auto it = string_values_.find(name);
if (it == string_values_.end()) {
return std::string();
}
return it->second;
}
int ArgParser::getInt(const std::string &name) const {
auto it = int_values_.find(name);
if (it == int_values_.end()) {
return 0;
}
return it->second;
}
std::string ArgParser::helpText() const {
std::ostringstream oss;
oss << "Usage: " << program_name_ << " [options]\n\n";
oss << "Options:\n";
oss << " -h, --help Show this help\n";
for (const auto &key : order_) {
auto m = meta_.find(key);
if (m == meta_.end()) {
continue;
}
oss << " --" << key << " <value>";
if (m->second.required) {
oss << " (required)";
}
oss << "\n";
oss << " " << m->second.help;
if (m->second.type == OptionType::kString) {
auto s = string_values_.find(key);
if (s != string_values_.end()) {
oss << " [default: '" << s->second << "']";
}
} else {
auto iv = int_values_.find(key);
if (iv != int_values_.end()) {
oss << " [default: " << iv->second << "]";
}
}
oss << "\n";
}
return oss.str();
}

63
tools/argparse.hpp Normal file
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@@ -0,0 +1,63 @@
#pragma once
#include <cstdint>
#include <string>
#include <unordered_map>
#include <vector>
class ArgParser {
public:
struct StringOption {
std::string name;
std::string default_value;
std::string help;
bool required;
};
struct IntOption {
std::string name;
int default_value;
std::string help;
bool required;
};
explicit ArgParser(std::string program_name);
void addString(const std::string &name,
const std::string &default_value,
const std::string &help,
bool required = false);
void addInt(const std::string &name,
int default_value,
const std::string &help,
bool required = false);
bool parse(int argc, char **argv, std::string *error);
bool has(const std::string &name) const;
std::string getString(const std::string &name) const;
int getInt(const std::string &name) const;
std::string helpText() const;
private:
enum class OptionType {
kString,
kInt
};
struct OptionMeta {
OptionType type;
std::string help;
bool required;
};
std::string program_name_;
std::vector<std::string> order_;
std::unordered_map<std::string, OptionMeta> meta_;
std::unordered_map<std::string, std::string> string_values_;
std::unordered_map<std::string, int> int_values_;
std::unordered_map<std::string, bool> provided_;
};

276
tools/digilent_jtag.cpp Normal file
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@@ -0,0 +1,276 @@
#include "digilent_jtag.hpp"
#include <algorithm>
#include <cstring>
#include <digilent/adept/dmgr.h>
#include <digilent/adept/djtg.h>
namespace {
constexpr int kDefaultIrBits = 6;
std::string ercToString(ERC erc) {
char code[cchErcMax] = {0};
char msg[cchErcMsgMax] = {0};
if (DmgrSzFromErc(erc, code, msg)) {
return std::string(code) + ": " + msg;
}
return "ERC=" + std::to_string(erc);
}
inline uint8_t getBit(const uint8_t* packed_bits, int bit_idx) {
return static_cast<uint8_t>((packed_bits[bit_idx / 8] >> (bit_idx % 8)) & 0x1u);
}
inline void setBit(uint8_t* packed_bits, int bit_idx, uint8_t bit) {
const uint8_t mask = static_cast<uint8_t>(1u << (bit_idx % 8));
if (bit & 0x1u) {
packed_bits[bit_idx / 8] |= mask;
} else {
packed_bits[bit_idx / 8] &= static_cast<uint8_t>(~mask);
}
}
} // namespace
DigilentJtag::DigilentJtag() : hif_(hifInvalid), enabled_port_(-1), last_error_() {}
DigilentJtag::~DigilentJtag() { close(); }
bool DigilentJtag::open(int port) {
close();
int count = 0;
if (!DmgrEnumDevices(&count)) {
return setErrorFromDmgr("DmgrEnumDevices");
}
if (count <= 0) {
return setError("open: no Digilent devices found");
}
DVC dvc{};
if (!DmgrGetDvc(0, &dvc)) {
return setErrorFromDmgr("DmgrGetDvc");
}
return open(std::string(dvc.szConn), port);
}
bool DigilentJtag::open(const std::string& selector, int port) {
close();
if (selector.empty()) {
return setError("open: selector is empty");
}
std::vector<char> sel(selector.begin(), selector.end());
sel.push_back('\0');
if (!DmgrOpen(&hif_, sel.data())) {
hif_ = hifInvalid;
return setErrorFromDmgr("DmgrOpen");
}
if (!DjtgEnableEx(hif_, static_cast<INT32>(port))) {
if (!DjtgEnable(hif_)) {
DmgrClose(hif_);
hif_ = hifInvalid;
return setErrorFromDmgr("DjtgEnableEx/DjtgEnable");
}
enabled_port_ = 0;
} else {
enabled_port_ = port;
}
last_error_.clear();
return true;
}
void DigilentJtag::close() {
if (hif_ != hifInvalid) {
(void)DjtgDisable(hif_);
(void)DmgrClose(hif_);
}
hif_ = hifInvalid;
enabled_port_ = -1;
}
bool DigilentJtag::isOpen() const { return hif_ != hifInvalid; }
HIF DigilentJtag::handle() const { return hif_; }
bool DigilentJtag::setSpeed(uint32_t requested_hz, uint32_t* actual_hz) {
if (!isOpen()) {
return setError("setSpeed: device not open");
}
DWORD actual = 0;
if (!DjtgSetSpeed(hif_, static_cast<DWORD>(requested_hz), &actual)) {
return setErrorFromDmgr("DjtgSetSpeed");
}
if (actual_hz) {
*actual_hz = static_cast<uint32_t>(actual);
}
last_error_.clear();
return true;
}
bool DigilentJtag::setChain(int chain, int ir_bits) {
uint32_t opcode = 0;
if (chain == 1) {
opcode = 0x02; // USER1 on Spartan-6
} else if (chain == 2) {
opcode = 0x03; // USER2 on Spartan-6
} else {
return setError("setChain: unsupported chain index (expected 1 or 2)");
}
return setInstruction(opcode, ir_bits);
}
bool DigilentJtag::setInstruction(uint32_t instruction, int ir_bits) {
if (!isOpen()) {
return setError("setInstruction: device not open");
}
if (ir_bits <= 0 || ir_bits > 64) {
return setError("setInstruction: ir_bits out of range");
}
// Force Test-Logic-Reset, then RTI.
uint8_t tlr = 0x3f; // 6 ones
if (!putTmsBits(&tlr, 6)) return false;
uint8_t rti = 0x00; // one zero
if (!putTmsBits(&rti, 1)) return false;
// RTI -> Shift-IR : 1,1,0,0 (LSB-first 0b0011)
uint8_t to_shift_ir = 0x03;
if (!putTmsBits(&to_shift_ir, 4)) return false;
std::vector<uint8_t> tx(static_cast<size_t>((ir_bits + 7) / 8), 0);
for (int i = 0; i < ir_bits && i < 64; ++i) {
if ((instruction >> i) & 0x1u) {
tx[static_cast<size_t>(i / 8)] |= static_cast<uint8_t>(1u << (i % 8));
}
}
std::vector<uint8_t> rx(tx.size(), 0);
if (ir_bits > 1) {
if (!putTdiBits(false, tx.data(), rx.data(), ir_bits - 1)) return false;
}
const uint8_t last_tx = getBit(tx.data(), ir_bits - 1);
uint8_t last_rx = 0;
if (!putTdiBits(true, &last_tx, &last_rx, 1)) return false;
// Exit1-IR -> Update-IR -> Idle: 1,0
uint8_t to_idle = 0x01;
if (!putTmsBits(&to_idle, 2)) return false;
last_error_.clear();
return true;
}
bool DigilentJtag::shiftData(const uint8_t* tx_bits, uint8_t* rx_bits, int bit_count) {
if (!isOpen()) {
return setError("shiftData: device not open");
}
if (bit_count <= 0) {
return setError("shiftData: bit_count must be > 0");
}
const size_t nbytes = static_cast<size_t>((bit_count + 7) / 8);
std::vector<uint8_t> tx_zeros;
if (!tx_bits) {
tx_zeros.assign(nbytes, 0);
tx_bits = tx_zeros.data();
}
std::vector<uint8_t> rx_tmp;
if (!rx_bits) {
rx_tmp.assign(nbytes, 0);
rx_bits = rx_tmp.data();
} else {
std::memset(rx_bits, 0, nbytes);
}
if (!enterShiftDR()) return false;
if (bit_count > 1) {
if (!putTdiBits(false, tx_bits, rx_bits, bit_count - 1)) return false;
}
const uint8_t tx_last = getBit(tx_bits, bit_count - 1);
uint8_t rx_last = 0;
if (!putTdiBits(true, &tx_last, &rx_last, 1)) return false;
setBit(rx_bits, bit_count - 1, rx_last & 0x1u);
if (!leaveShiftToIdle()) return false;
last_error_.clear();
return true;
}
bool DigilentJtag::shiftData(const std::vector<uint8_t>& tx_bits, std::vector<uint8_t>* rx_bits, int bit_count) {
if (bit_count <= 0) {
return setError("shiftData(vector): bit_count must be > 0");
}
const size_t nbytes = static_cast<size_t>((bit_count + 7) / 8);
if (tx_bits.size() < nbytes) {
return setError("shiftData(vector): tx_bits is smaller than required bit_count");
}
std::vector<uint8_t> local_rx;
local_rx.assign(nbytes, 0);
if (!shiftData(tx_bits.data(), local_rx.data(), bit_count)) {
return false;
}
if (rx_bits) {
*rx_bits = std::move(local_rx);
}
return true;
}
const std::string& DigilentJtag::lastError() const { return last_error_; }
bool DigilentJtag::enterShiftDR() {
// Idle -> Select-DR -> Capture-DR -> Shift-DR : 1,0,0
uint8_t to_shift_dr = 0x01;
return putTmsBits(&to_shift_dr, 3);
}
bool DigilentJtag::leaveShiftToIdle() {
// Exit1-DR -> Update-DR -> Idle : 1,0
uint8_t to_idle = 0x01;
return putTmsBits(&to_idle, 2);
}
bool DigilentJtag::putTmsBits(const uint8_t* tms_bits, int bit_count) {
if (!DjtgPutTmsBits(hif_, fFalse, const_cast<uint8_t*>(tms_bits), nullptr, static_cast<DWORD>(bit_count), fFalse)) {
return setErrorFromDmgr("DjtgPutTmsBits");
}
return true;
}
bool DigilentJtag::putTdiBits(bool tms, const uint8_t* tx_bits, uint8_t* rx_bits, int bit_count) {
if (!DjtgPutTdiBits(
hif_,
tms ? fTrue : fFalse,
const_cast<uint8_t*>(tx_bits),
rx_bits,
static_cast<DWORD>(bit_count),
fFalse)) {
return setErrorFromDmgr("DjtgPutTdiBits");
}
return true;
}
bool DigilentJtag::setError(const std::string& msg) {
last_error_ = msg;
return false;
}
bool DigilentJtag::setErrorFromDmgr(const std::string& where) {
last_error_ = where + " failed: " + ercToString(DmgrGetLastError());
return false;
}

52
tools/digilent_jtag.hpp Normal file
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@@ -0,0 +1,52 @@
#pragma once
#include <cstdint>
#include <string>
#include <vector>
#include <digilent/adept/dpcdecl.h>
class DigilentJtag {
public:
DigilentJtag();
~DigilentJtag();
DigilentJtag(const DigilentJtag&) = delete;
DigilentJtag& operator=(const DigilentJtag&) = delete;
bool open(int port = 0);
bool open(const std::string& selector, int port = 0);
void close();
bool isOpen() const;
HIF handle() const;
bool setSpeed(uint32_t requested_hz, uint32_t* actual_hz = nullptr);
// For Spartan-6 style USER chains:
// chain=1 -> USER1 opcode 0x02, chain=2 -> USER2 opcode 0x03
bool setChain(int chain, int ir_bits = 6);
bool setInstruction(uint32_t instruction, int ir_bits);
// Shifts one DR transaction from Idle -> ShiftDR -> UpdateDR -> Idle.
// tx_bits is LSB-first in packed byte form.
// rx_bits, when non-null, receives captured TDO bits in the same packing.
bool shiftData(const uint8_t* tx_bits, uint8_t* rx_bits, int bit_count);
bool shiftData(const std::vector<uint8_t>& tx_bits, std::vector<uint8_t>* rx_bits, int bit_count);
const std::string& lastError() const;
private:
bool enterShiftDR();
bool leaveShiftToIdle();
bool putTmsBits(const uint8_t* tms_bits, int bit_count);
bool putTdiBits(bool tms, const uint8_t* tx_bits, uint8_t* rx_bits, int bit_count);
bool setError(const std::string& msg);
bool setErrorFromDmgr(const std::string& where);
HIF hif_;
int enabled_port_;
std::string last_error_;
};

90
tools/test.cpp Normal file
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@@ -0,0 +1,90 @@
#include "digilent_jtag.hpp"
#include "argparse.hpp"
#include <algorithm>
#include <cstdio>
#include <string>
void write(DigilentJtag &jtag, uint32_t addr, uint8_t data, bool reset){
uint8_t d[6], din[6];
d[0] = data;
d[1] = (uint8_t)addr;
d[2] = (uint8_t)(addr>>8);
d[3] = (uint8_t)(addr>>16);
d[4] = (uint8_t)(addr>>24);
d[5] = ((reset) ? 1 : 0) | 0x2; // <we><rst>
jtag.shiftData(d, din, 42);
}
uint8_t read(DigilentJtag &jtag, uint32_t addr, bool reset){
uint8_t d[6], din[6];
d[0] = 0xff;
d[1] = (uint8_t)addr;
d[2] = (uint8_t)(addr>>8);
d[3] = (uint8_t)(addr>>16);
d[4] = (uint8_t)(addr>>24);
d[5] = ((reset) ? 1 : 0); // <we><rst>
jtag.shiftData(d, din, 42);
// Read back
jtag.shiftData(d, din, 42);
return din[0];
}
int main(int argc, char** argv){
ArgParser parser(argc > 0 ? argv[0] : "test");
parser.addString("write", "", "file to write");
std::string parse_error;
if (!parser.parse(argc, argv, &parse_error)) {
if (parse_error == "help") {
std::printf("%s", parser.helpText().c_str());
return 0;
}
std::printf("Argument error: %s\n\n", parse_error.c_str());
std::printf("%s", parser.helpText().c_str());
return -1;
}
const std::string arg_write = parser.getString("write");
DigilentJtag jtag;
if(!jtag.open()){
printf("Could not open programmer\r\n");
return -1;
}
jtag.setChain(1);
// Start reset
read(jtag, 0, true);
if(arg_write!=""){
uint32_t addr = 0;
uint8_t buf[32];
int nr;
FILE* f = fopen(arg_write.c_str(), "rb");
if(!f){
goto end;
}
do{
nr = fread(buf, 1, 32, f);
for(int i=0; i<32; i++){
write(jtag, addr, buf[i], true);
addr++;
}
}while(nr>0);
fclose(f);
}
end:
// End reset
read(jtag, 0, false);
jtag.close();
return 0;
}