55 lines
1.3 KiB
Verilog
55 lines
1.3 KiB
Verilog
`default_nettype none
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`include "../util/clog2.vh"
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module serving_ram_dp
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#(// Memory parameters
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parameter depth = 256,
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parameter aw = `CLOG2(depth),
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parameter memfile = "",
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parameter sim = 1'b0)
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(
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// CPU port (compatible with serving_ram)
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input wire i_clk,
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input wire [aw-1:0] i_waddr,
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input wire [7:0] i_wdata,
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input wire i_wen,
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input wire [aw-1:0] i_raddr,
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output reg [7:0] o_rdata,
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// Debug/programming port
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input wire i_dbg_clk,
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input wire [aw-1:0] i_dbg_addr,
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input wire [7:0] i_dbg_wdata,
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input wire i_dbg_wen,
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output wire [7:0] o_dbg_rdata
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);
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reg [7:0] mem [0:depth-1] /* verilator public */;
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always @(posedge i_clk) begin
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if (i_wen)
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mem[i_waddr] <= i_wdata;
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o_rdata <= mem[i_raddr];
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end
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always @(posedge i_dbg_clk) begin
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if (i_dbg_wen)
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mem[i_dbg_addr] <= i_dbg_wdata;
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end
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// Asynchronous debug read simplifies JTAG readback logic.
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assign o_dbg_rdata = mem[i_dbg_addr];
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integer i;
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initial begin
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if (sim == 1'b1) begin
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for (i = 0; i < depth; i = i + 1)
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mem[i] = 8'h00;
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end
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if (|memfile) begin
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$display("Preloading %m from %s", memfile);
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$readmemh(memfile, mem);
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end
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end
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endmodule
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