`default_nettype none
`include "../util/clog2.vh"

module serving_ram_dp
  #(// Memory parameters
    parameter depth = 256,
    parameter aw = `CLOG2(depth),
    parameter memfile = "",
    parameter sim = 1'b0)
   (
    // CPU port (compatible with serving_ram)
    input wire           i_clk,
    input wire [aw-1:0]  i_waddr,
    input wire [7:0]     i_wdata,
    input wire           i_wen,
    input wire [aw-1:0]  i_raddr,
    output reg [7:0]     o_rdata,

    // Debug/programming port
    input wire           i_dbg_clk,
    input wire [aw-1:0]  i_dbg_addr,
    input wire [7:0]     i_dbg_wdata,
    input wire           i_dbg_wen,
    output wire [7:0]    o_dbg_rdata
    );

   reg [7:0] mem [0:depth-1] /* verilator public */;

   always @(posedge i_clk) begin
      if (i_wen)
        mem[i_waddr] <= i_wdata;
      o_rdata <= mem[i_raddr];
   end

   always @(posedge i_dbg_clk) begin
      if (i_dbg_wen)
        mem[i_dbg_addr] <= i_dbg_wdata;
   end

   // Asynchronous debug read simplifies JTAG readback logic.
   assign o_dbg_rdata = mem[i_dbg_addr];

   integer i;
   initial begin
      if (sim == 1'b1) begin
         for (i = 0; i < depth; i = i + 1)
           mem[i] = 8'h00;
      end
      if (|memfile) begin
         $display("Preloading %m from %s", memfile);
         $readmemh(memfile, mem);
      end
   end
endmodule