vibed jtagram with script as drop in replacement of serving_ram

boards/mimas_v1/constraints.ucf

@@ -2,9 +2,6 @@
 NET "aclk" LOC = P126;
 NET "aclk" TNM_NET = "SYS_CLK_PIN";
 TIMESPEC TS_SYS_CLK_PIN = PERIOD "SYS_CLK_PIN" 10 ns HIGH 50 %;
-# Generated clocks
-NET "clk_15" TNM_NET = "SYS_CLK_15";
-TIMESPEC TS_SYS_CLK_15 = PERIOD "SYS_CLK_15" 13.334 ns HIGH 50%;
 
 # Boards button row
 NET "aresetn" LOC = P120;

project.cfg

@@ -4,23 +4,17 @@ version             = 0.1
 out_dir             = out
 build_dir           = build
 
-[server]
-hostname            = localhost
-port                = 2020
-privkey             = /home/joppe/.ssh/id_rsa
-pubkey              = /home/joppe/.ssh/id_rsa.pub
-
 [target.synth]
 toolchain           = ISE
 ise_settings        = /opt/Xilinx/14.7/ISE_DS/settings64.sh
-# Toolchain settings
 family              = spartan6
 device              = xc6slx9
 package             = tqg144
 speedgrade          = -2
 toplevel            = top_generic
 xst_opts            = -vlgincdir rtl/util
-files_verilog       = rtl/toplevel/top_generic.v
+files_verilog       = rtl/util/conv.vh
+                      rtl/toplevel/top_generic.v
                       rtl/core/nco_q15.v
                       rtl/core/sigmadelta_sampler.v
                       rtl/core/sigmadelta_rcmodel_q15.v
@@ -30,31 +24,6 @@ files_verilog       = rtl/toplevel/top_generic.v
                       rtl/core/decimate_by_r_q15.v
                       rtl/arch/spartan-6/lvds_comparator.v
                       rtl/arch/spartan-6/clk_gen.v
-files_con           = boards/mimas_v1/constraints.ucf
-files_other         = rtl/util/conv.vh
-                      rtl/util/rc_alpha_q15.vh
-
-[target.ip]
-toolchain           = ISE_IP
-family              = spartan6
-device              = xc6slx9
-package             = tqg144
-speedgrade          = -2
-files_xco           = boards/mimas_v1/ip/clk_gen.xco
-
-
-[target.serv]
-toolchain           = ISE
-ise_settings        = /opt/Xilinx/14.7/ISE_DS/settings64.sh
-family              = spartan6
-device              = xc6slx9
-package             = tqg144
-speedgrade          = -2
-toplevel            = top_generic
-xst_opts            = -vlgincdir rtl
-files_con           = boards/mimas_v1/constraints.ucf
-files_other         = sw/blinky/blinky.hex
-files_verilog       = rtl/util/clog2.vh
                       rtl/serv/serv_aligner.v
                       rtl/serv/serv_alu.v
                       rtl/serv/serv_bufreg.v
@@ -78,10 +47,23 @@ files_verilog       = rtl/util/clog2.vh
                       rtl/serv/servile_rf_mem_if.v
                       rtl/serv/servile.v
                       rtl/serv/serving_ram.v
-                      # sim/overrides/serving_ram.v
                       rtl/serv/serving.v
                       rtl/wb/wb_gpio.v
-                      rtl/toplevel/top_serv.v
+                      rtl/wb/wb_gpio_banks.v
+                      rtl/core/soclet.v
+files_con           = boards/mimas_v1/constraints.ucf
+files_other         = rtl/util/rc_alpha_q15.vh
+                      rtl/util/clog2.vh
+                      sw/blinky/blinky.hex
+
+[target.ip]
+toolchain           = ISE_IP
+ise_settings        = /opt/Xilinx/14.7/ISE_DS/settings64.sh
+family              = spartan6
+device              = xc6slx9
+package             = tqg144
+speedgrade          = -2
+files_def           = boards/mimas_v1/ip/clk_gen.xco
 
 [target.sim]
 toolchain           = iverilog
@@ -101,4 +83,4 @@ files_verilog       = sim/tb/tb_nco_q15.v
                       sim/overrides/sigmadelta_sampler.v
                       sim/overrides/clk_gen.v
 files_other         = rtl/util/conv.vh
-                      rtl/util/rc_alpha_q15.vh
+                      rtl/util/rc_alpha_q15.vh

rtl/arch/spartan-6/clk_gen.v

@@ -67,9 +67,9 @@
 (* CORE_GENERATION_INFO = "clk_gen,clk_wiz_v3_6,{component_name=clk_gen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
 module clk_gen
  (// Clock in ports
-  input         clk_in,
+  input  wire   clk_in,
   // Clock out ports
-  output        clk_out_15
+  output wire   clk_out_15
  );
 
   // Input buffering
@@ -78,6 +78,7 @@ module clk_gen
   //  (.O (clkin1),
     // .I (clk_in));
 
+  wire clkin1;
   assign clkin1 = clk_in;
 
   // Clocking primitive
@@ -145,4 +146,3 @@ module clk_gen
 
 
 endmodule
-

rtl/arch/spartan-6/jtag_tap_spartan6.v

@@ -0,0 +1,49 @@
+`default_nettype none
+
+// Spartan-6 JTAG TAP wrapper with an architecture-neutral interface.
+// Re-implement this module for other FPGA families with the same port list.
+module jtag_tap_spartan6
+  #(parameter USER_CHAIN = 1)
+   (
+    output wire o_drck,
+    output wire o_capture,
+    output wire o_shift,
+    output wire o_update,
+    output wire o_reset,
+    output wire o_sel,
+    output wire o_tdi,
+    input wire  i_tdo
+    );
+
+   wire drck1;
+   wire drck2;
+   wire sel1;
+   wire sel2;
+   wire tdo1;
+   wire tdo2;
+
+   localparam USE_CHAIN2 = (USER_CHAIN == 2);
+
+   assign o_drck = USE_CHAIN2 ? drck2 : drck1;
+   assign o_sel  = USE_CHAIN2 ? sel2  : sel1;
+   assign tdo1   = USE_CHAIN2 ? 1'b0  : i_tdo;
+   assign tdo2   = USE_CHAIN2 ? i_tdo : 1'b0;
+
+   BSCAN_SPARTAN6
+     #(.JTAG_CHAIN(USER_CHAIN))
+   bscan_spartan6
+     (
+      .CAPTURE(o_capture),
+      .DRCK1(drck1),
+      .DRCK2(drck2),
+      .RESET(o_reset),
+      .SEL1(sel1),
+      .SEL2(sel2),
+      .SHIFT(o_shift),
+      .TDI(o_tdi),
+      .UPDATE(o_update),
+      .TDO1(tdo1),
+      .TDO2(tdo2)
+      );
+
+endmodule

rtl/core/soclet.v

@@ -0,0 +1,77 @@
+`timescale 1ns/1ps
+
+module soclet #(
+    parameter memfile = "",
+    parameter memsize = 8192,
+    parameter sim = 1'b0
+)(
+    input wire i_clk,
+    input wire i_rst,
+
+    input wire [31:0] i_GPI_A,
+    input wire [31:0] i_GPI_B,
+    input wire [31:0] i_GPI_C,
+    input wire [31:0] i_GPI_D,
+
+    output wire [31:0] o_GPO_A,
+    output wire [31:0] o_GPO_B,
+    output wire [31:0] o_GPO_C,
+    output wire [31:0] o_GPO_D
+);
+
+    wire [31:0] wb_adr;
+    wire [31:0] wb_dat;
+    wire [31:0] wb_rdt;
+    wire [3:0] wb_sel;
+    wire wb_we;
+    wire wb_stb;
+    wire wb_ack;
+
+    wire [4*32-1:0] GPO;
+    wire [4*32-1:0] GPI;
+    assign o_GPO_A = GPO[32*1-1:32*0];
+    assign o_GPO_B = GPO[32*2-1:32*1];
+    assign o_GPO_C = GPO[32*3-1:32*2];
+    assign o_GPO_D = GPO[32*4-1:32*3];
+    assign GPI[32*1-1:32*0] = i_GPI_A;
+    assign GPI[32*2-1:32*1] = i_GPI_B;
+    assign GPI[32*3-1:32*2] = i_GPI_C;
+    assign GPI[32*4-1:32*3] = i_GPI_D;
+
+    serving #(
+        .memfile(memfile),
+        .memsize(memsize),
+        .sim(sim),
+        .RESET_STRATEGY("MINI"),
+        .WITH_CSR(1)
+    ) serv (
+        .i_clk(i_clk),
+        .i_rst(i_rst),
+        .i_timer_irq(1'b0),
+        .i_wb_rdt(wb_rdt),
+        .i_wb_ack(wb_ack),
+        .o_wb_adr(wb_adr),
+        .o_wb_dat(wb_dat),
+        .o_wb_sel(wb_sel),
+        .o_wb_we(wb_we),
+        .o_wb_stb(wb_stb)
+    );
+
+    wb_gpio_banks #(
+      .BASE_ADDR(32'h40000000),
+      .NUM_BANKS(4)
+    ) gpio (
+        .i_wb_clk(i_clk),
+        .i_wb_rst(i_rst),
+        .i_wb_dat(wb_dat),
+        .i_wb_adr(wb_adr),
+        .i_wb_we(wb_we),
+        .i_wb_stb(wb_stb),
+        .i_wb_sel(wb_sel),
+        .i_gpio(GPI),
+        .o_wb_rdt(wb_rdt),
+        .o_wb_ack(wb_ack),
+        .o_gpio(GPO)
+    );
+
+endmodule

rtl/serv/serv_rf_ram.v

@@ -4,15 +4,16 @@
  * SPDX-FileCopyrightText: 2019 Olof Kindgren <olof@award-winning.me>
  * SPDX-License-Identifier: ISC
  */
+`include "../util/clog2.vh"
 module serv_rf_ram
   #(parameter width=0,
     parameter csr_regs=4,
     parameter depth=32*(32+csr_regs)/width)
    (input wire i_clk,
-    input wire [$clog2(depth)-1:0] i_waddr,
+    input wire [`CLOG2(depth)-1:0] i_waddr,
     input wire [width-1:0] 	   i_wdata,
     input wire 			   i_wen,
-    input wire [$clog2(depth)-1:0] i_raddr,
+    input wire [`CLOG2(depth)-1:0] i_raddr,
     input wire			   i_ren,
     output wire [width-1:0] 	   o_rdata);
 
@@ -28,7 +29,7 @@ module serv_rf_ram
    /* Reads from reg x0 needs to return 0
     Check that the part of the read address corresponding to the register
     is zero and gate the output
-    width LSB of reg index $clog2(width)
+    width LSB of reg index `CLOG2(width)
     2     4                1
     4     3                2
     8     2                3
@@ -38,7 +39,7 @@ module serv_rf_ram
    reg regzero;
 
    always @(posedge i_clk)
-     regzero <= !(|i_raddr[$clog2(depth)-1:5-$clog2(width)]);
+     regzero <= !(|i_raddr[`CLOG2(depth)-1:5-`CLOG2(width)]);
 
    assign o_rdata = rdata & ~{width{regzero}};
 

rtl/serv/serv_rf_ram_if.v

@@ -5,7 +5,7 @@
  * SPDX-License-Identifier: ISC
  */
 `default_nettype none
-// `include "../util/clog2.vh"
+`include "../util/clog2.vh"
 module serv_rf_ram_if
   #(//Data width. Adjust to preferred width of SRAM data interface
     parameter width=8,
@@ -22,8 +22,8 @@ module serv_rf_ram_if
 
     //Internal parameters calculated from above values. Do not change
     parameter B=W-1,
-    parameter raw=clog2(32+csr_regs), //Register address width
-    parameter l2w=clog2(width), //log2 of width
+    parameter raw=`CLOG2(32+csr_regs), //Register address width
+    parameter l2w=`CLOG2(width), //log2 of width
     parameter aw=5+raw-l2w) //Address width
   (
    //SERV side
@@ -51,8 +51,8 @@ module serv_rf_ram_if
    input wire [width-1:0]  i_rdata);
 
    localparam ratio = width/W;
-   localparam CMSB = 4-clog2(W); //Counter MSB
-   localparam l2r  = clog2(ratio);
+   localparam CMSB = 4-`CLOG2(W); //Counter MSB
+   localparam l2r  = `CLOG2(ratio);
 
    reg 				   rgnt;
    assign o_ready = rgnt | i_wreq;

rtl/serv/serv_rf_top.v

@@ -5,6 +5,7 @@
  * SPDX-License-Identifier: ISC
  */
 `default_nettype none
+`include "../util/clog2.vh"
 
 module serv_rf_top
   #(parameter RESET_PC = 32'd0,
@@ -37,7 +38,7 @@ module serv_rf_top
     parameter WITH_CSR = 1,
     parameter W        = 1,
     parameter RF_WIDTH = W * 2,
-	parameter RF_L2D   = $clog2((32+(WITH_CSR*4))*32/RF_WIDTH))
+	parameter RF_L2D   = `CLOG2((32+(WITH_CSR*4))*32/RF_WIDTH))
   (
    input wire 	      clk,
    input wire 	      i_rst,

rtl/serv/serv_synth_wrapper.v

@@ -5,6 +5,7 @@
  * SPDX-License-Identifier: ISC
  */
 `default_nettype none
+`include "../util/clog2.vh"
 
 module serv_synth_wrapper
   #(
@@ -22,7 +23,7 @@ module serv_synth_wrapper
     parameter RESET_STRATEGY = "MINI",
     parameter WITH_CSR = 1,
     parameter RF_WIDTH = 2,
-	parameter RF_L2D   = $clog2((32+(WITH_CSR*4))*32/RF_WIDTH))
+	parameter RF_L2D   = `CLOG2((32+(WITH_CSR*4))*32/RF_WIDTH))
   (
    input wire 		      clk,
    input wire 		      i_rst,

rtl/serv/servile.v

@@ -6,6 +6,7 @@
  */
 
 `default_nettype none
+`include "../util/clog2.vh"
 module servile
   #(
     parameter	    width = 1,
@@ -20,7 +21,7 @@ module servile
     //Internally calculated. Do not touch
     parameter	    B = width-1,
     parameter	    regs = 32+with_csr*4,
-    parameter	    rf_l2d = $clog2(regs*32/rf_width))
+    parameter	    rf_l2d = `CLOG2(regs*32/rf_width))
   (
    input wire		      i_clk,
    input wire		      i_rst,
@@ -77,14 +78,14 @@ module servile
 
    wire 		   rf_wreq;
    wire 		   rf_rreq;
-   wire [$clog2(regs)-1:0] wreg0;
-   wire [$clog2(regs)-1:0] wreg1;
+   wire [`CLOG2(regs)-1:0] wreg0;
+   wire [`CLOG2(regs)-1:0] wreg1;
    wire 		   wen0;
    wire 		   wen1;
    wire [B:0]		   wdata0;
    wire [B:0]		   wdata1;
-   wire [$clog2(regs)-1:0] rreg0;
-   wire [$clog2(regs)-1:0] rreg1;
+   wire [`CLOG2(regs)-1:0] rreg0;
+   wire [`CLOG2(regs)-1:0] rreg1;
    wire 		   rf_ready;
    wire [B:0]		   rdata0;
    wire [B:0]		   rdata1;

rtl/serv/servile_rf_mem_if.v

@@ -6,14 +6,15 @@
  */
 
 `default_nettype none
+`include "../util/clog2.vh"
 module servile_rf_mem_if
   #(//Memory parameters
     parameter depth = 256,
     //RF parameters
     parameter rf_regs = 32,
     //Internally calculated. Do not touch
-    parameter rf_depth = $clog2(rf_regs*4),
-    parameter aw = $clog2(depth))
+    parameter rf_depth = `CLOG2(rf_regs*4),
+    parameter aw = `CLOG2(depth))
    (
     input wire		      i_clk,
     input wire		      i_rst,

rtl/serv/serving.v

@@ -18,6 +18,7 @@
  */
 
 `default_nettype none
+`include "../util/clog2.vh"
 module serving
   (
    input wire 	      i_clk,
@@ -56,16 +57,17 @@ module serving
    wire [rf_width-1:0] rf_rdata;
    wire		       rf_ren;
 
-   wire [$clog2(memsize)-1:0] sram_waddr;
+   wire [`CLOG2(memsize)-1:0] sram_waddr;
    wire [rf_width-1:0] sram_wdata;
    wire 	       sram_wen;
-   wire [$clog2(memsize)-1:0] sram_raddr;
+   wire [`CLOG2(memsize)-1:0] sram_raddr;
    wire [rf_width-1:0] sram_rdata;
    wire		       sram_ren;
 
    serving_ram
      #(.memfile (memfile),
-       .depth   (memsize))
+       .depth   (memsize),
+       .sim     (sim))
    ram
      (// Wishbone interface
       .i_clk (i_clk),
@@ -98,7 +100,7 @@ module serving
       .i_sram_rdata (sram_rdata),
       .o_sram_ren   (sram_ren),
 
-      .i_wb_adr (wb_mem_adr[$clog2(memsize)-1:2]),
+      .i_wb_adr (wb_mem_adr[`CLOG2(memsize)-1:2]),
       .i_wb_stb (wb_mem_stb),
       .i_wb_we  (wb_mem_we) ,
       .i_wb_sel (wb_mem_sel),

rtl/serv/serving_ram.v

@@ -18,28 +18,37 @@
  */
 
 `default_nettype none
+`include "../util/clog2.vh"
 module serving_ram
   #(//Memory parameters
-    parameter depth = 256,
-    parameter aw    = $clog2(depth),
-    parameter memfile = "")
+	parameter depth = 256,
+	parameter aw    = `CLOG2(depth),
+	parameter memfile = "",
+	parameter sim = 1'b0)
    (input wire		i_clk,
-    input wire [aw-1:0]	i_waddr,
-    input wire [7:0]	i_wdata,
-    input wire		i_wen,
-    input wire [aw-1:0]	i_raddr,
-    output reg [7:0]	o_rdata);
+	input wire [aw-1:0]	i_waddr,
+	input wire [7:0]	i_wdata,
+	input wire		i_wen,
+	input wire [aw-1:0]	i_raddr,
+	output reg [7:0]	o_rdata);
 
-   reg [7:0]		mem [0:depth-1] /* verilator public */;
+   	reg [7:0]		mem [0:depth-1] /* verilator public */;
 
-   always @(posedge i_clk) begin
-      if (i_wen) mem[i_waddr]   <= i_wdata;
-      o_rdata <= mem[i_raddr];
+	always @(posedge i_clk) begin
+		if (i_wen) mem[i_waddr]   <= i_wdata;
+		o_rdata <= mem[i_raddr];
+	end
+
+	integer i;
+   	initial begin
+		if(sim==1'b1) begin
+			for (i = 0; i < depth; i = i + 1)
+				mem[i] = 8'h00;
+
+		end
+		if(|memfile) begin
+			$display("Preloading %m from %s", memfile);
+			$readmemh(memfile, mem);
+		end
    end
-
-   initial
-     if(|memfile) begin
-	$display("Preloading %m from %s", memfile);
-	$readmemh(memfile, mem);
-     end
 endmodule

rtl/serv/serving_ram_dp.v

@@ -0,0 +1,54 @@
+`default_nettype none
+`include "../util/clog2.vh"
+
+module serving_ram_dp
+  #(// Memory parameters
+    parameter depth = 256,
+    parameter aw = `CLOG2(depth),
+    parameter memfile = "",
+    parameter sim = 1'b0)
+   (
+    // CPU port (compatible with serving_ram)
+    input wire           i_clk,
+    input wire [aw-1:0]  i_waddr,
+    input wire [7:0]     i_wdata,
+    input wire           i_wen,
+    input wire [aw-1:0]  i_raddr,
+    output reg [7:0]     o_rdata,
+
+    // Debug/programming port
+    input wire           i_dbg_clk,
+    input wire [aw-1:0]  i_dbg_addr,
+    input wire [7:0]     i_dbg_wdata,
+    input wire           i_dbg_wen,
+    output wire [7:0]    o_dbg_rdata
+    );
+
+   reg [7:0] mem [0:depth-1] /* verilator public */;
+
+   always @(posedge i_clk) begin
+      if (i_wen)
+        mem[i_waddr] <= i_wdata;
+      o_rdata <= mem[i_raddr];
+   end
+
+   always @(posedge i_dbg_clk) begin
+      if (i_dbg_wen)
+        mem[i_dbg_addr] <= i_dbg_wdata;
+   end
+
+   // Asynchronous debug read simplifies JTAG readback logic.
+   assign o_dbg_rdata = mem[i_dbg_addr];
+
+   integer i;
+   initial begin
+      if (sim == 1'b1) begin
+         for (i = 0; i < depth; i = i + 1)
+           mem[i] = 8'h00;
+      end
+      if (|memfile) begin
+         $display("Preloading %m from %s", memfile);
+         $readmemh(memfile, mem);
+      end
+   end
+endmodule

rtl/serv/serving_ram_jtag.v

@@ -0,0 +1,65 @@
+`default_nettype none
+`include "../util/clog2.vh"
+
+// Drop-in serving RAM variant with USER JTAG programming access.
+module serving_ram_jtag
+  #(
+    parameter depth = 256,
+    parameter aw = `CLOG2(depth),
+    parameter memfile = "",
+    parameter sim = 1'b0,
+    parameter USER_CHAIN = 1
+    )
+   (
+    input wire          i_clk,
+    input wire [aw-1:0] i_waddr,
+    input wire [7:0]    i_wdata,
+    input wire          i_wen,
+    input wire [aw-1:0] i_raddr,
+    output wire [7:0]   o_rdata
+    );
+
+   wire          dbg_clk;
+   wire [aw-1:0] dbg_addr;
+   wire [7:0]    dbg_wdata;
+   wire          dbg_wen;
+   wire [7:0]    dbg_rdata;
+
+   serving_ram_dp
+     #(
+       .depth(depth),
+       .aw(aw),
+       .memfile(memfile),
+       .sim(sim)
+       )
+   i_serving_ram_dp
+     (
+      .i_clk(i_clk),
+      .i_waddr(i_waddr),
+      .i_wdata(i_wdata),
+      .i_wen(i_wen),
+      .i_raddr(i_raddr),
+      .o_rdata(o_rdata),
+      .i_dbg_clk(dbg_clk),
+      .i_dbg_addr(dbg_addr),
+      .i_dbg_wdata(dbg_wdata),
+      .i_dbg_wen(dbg_wen),
+      .o_dbg_rdata(dbg_rdata)
+      );
+
+   serving_ram_jtag_bridge
+     #(
+       .depth(depth),
+       .aw(aw),
+       .USER_CHAIN(USER_CHAIN)
+       )
+   i_serving_ram_jtag_bridge
+     (
+      .o_ram_clk(dbg_clk),
+      .o_ram_addr(dbg_addr),
+      .o_ram_wdata(dbg_wdata),
+      .o_ram_wen(dbg_wen),
+      .i_ram_rdata(dbg_rdata)
+      );
+
+endmodule

rtl/serv/serving_ram_jtag_bridge.v

@@ -0,0 +1,107 @@
+`default_nettype none
+`include "../util/clog2.vh"
+
+// Simple USER JTAG data-register protocol (LSB-first):
+// bit[0]              : write_enable (1=write, 0=read/select)
+// bit[32:1]           : 32-bit address
+// bit[40:33]          : write data
+//
+// On UPDATE:
+// - write command: writes byte to RAM
+// - read command : updates current read address for next CAPTURE/SHIFT readback
+// - RAM uses the lower aw address bits from the 32-bit protocol address
+//
+// On CAPTURE, readback register loads:
+// bit[0]              : valid (always 1)
+// bit[8:1]            : read data at current read address
+// remaining bits      : zero
+module serving_ram_jtag_bridge
+  #(
+    parameter depth = 256,
+    parameter aw = `CLOG2(depth),
+    parameter USER_CHAIN = 1
+    )
+   (
+    output wire          o_ram_clk,
+    output wire [aw-1:0] o_ram_addr,
+    output wire [7:0]    o_ram_wdata,
+    output wire          o_ram_wen,
+    input wire [7:0]     i_ram_rdata
+    );
+
+   localparam integer JTAG_AW = 32;
+   localparam integer FRAME_W = 1 + JTAG_AW + 8;
+   localparam integer PAD_W = FRAME_W - 9;
+
+   wire tap_drck;
+   wire tap_shift;
+   wire tap_update;
+   wire tap_reset;
+   wire tap_sel;
+   wire tap_tdi;
+   wire tap_tdo;
+
+   reg [FRAME_W-1:0] shift_in;
+   reg [FRAME_W-1:0] shift_out;
+   reg [aw-1:0]      read_addr;
+   reg               shift_active_d;
+
+   wire              cmd_write;
+   wire [JTAG_AW-1:0] cmd_addr;
+   wire [aw-1:0]      cmd_addr_ram;
+   wire [7:0]        cmd_wdata;
+
+   assign cmd_write = shift_in[0];
+   assign cmd_addr  = shift_in[JTAG_AW:1];
+   assign cmd_wdata = shift_in[JTAG_AW+8:JTAG_AW+1];
+   assign cmd_addr_ram = cmd_addr[aw-1:0];
+
+   // Update command shift register and shift response out on DRCK.
+   // Readback data is loaded on the first shift pulse of a DR scan.
+   always @(posedge tap_drck or posedge tap_reset) begin
+      if (tap_reset) begin
+         shift_in        <= {FRAME_W{1'b0}};
+         shift_out       <= {FRAME_W{1'b0}};
+         shift_active_d  <= 1'b0;
+      end else if (tap_sel && tap_shift) begin
+         if (!shift_active_d)
+           shift_out <= {{PAD_W{1'b0}}, i_ram_rdata, 1'b1};
+         else
+           shift_out <= {1'b0, shift_out[FRAME_W-1:1]};
+         shift_in       <= {tap_tdi, shift_in[FRAME_W-1:1]};
+         shift_active_d <= 1'b1;
+      end else begin
+         shift_active_d <= 1'b0;
+      end
+   end
+
+   // Read command selects the address for the next capture.
+   always @(posedge tap_update or posedge tap_reset) begin
+      if (tap_reset)
+        read_addr <= {aw{1'b0}};
+      else if (tap_sel && !cmd_write)
+        read_addr <= cmd_addr_ram;
+   end
+
+   assign o_ram_clk   = tap_update;
+   assign o_ram_wen   = tap_update & tap_sel & cmd_write;
+   assign o_ram_wdata = cmd_wdata;
+   assign o_ram_addr  = tap_update ? cmd_addr_ram : read_addr;
+
+   assign tap_tdo = shift_out[0];
+
+   jtag_tap_spartan6
+     #(.USER_CHAIN(USER_CHAIN))
+   i_jtag_tap
+     (
+      .o_drck(tap_drck),
+      .o_capture(),
+      .o_shift(tap_shift),
+      .o_update(tap_update),
+      .o_reset(tap_reset),
+      .o_sel(tap_sel),
+      .o_tdi(tap_tdi),
+      .i_tdo(tap_tdo)
+      );
+
+endmodule

rtl/toplevel/top_generic.v

@@ -22,45 +22,43 @@ module top_generic(
         .clk_out_15(clk_15)
     );
 
-    reg [11:0] count;
-    localparam integer DIV_MAX = 100_000 - 1; // 1 ms tick at 100 MHz
-    reg [16:0] div_counter = 0;               // enough bits for 100k (2^17=131072)
-    reg [31:0] freq;
-    always @(posedge aclk) begin
-        if (!aresetn) begin
-            div_counter <= 0;
-            count <= 0;
-        end else begin
-            if (div_counter == DIV_MAX) begin
-                div_counter <= 0;
-                if (count == 12'd3999)
-                    count <= 0;               // wrap at 4000
-                else
-                    count <= count + 1'b1;    // increment every 1 ms
-            end else begin
-                div_counter <= div_counter + 1'b1;
-            end
-        end
-        freq <= count;
-    end
+    wire [31:0] GPIO_A;
+    wire [31:0] GPIO_B;
+    wire [31:0] GPIO_C;
+    wire [31:0] GPIO_D;
+
+    soclet #(
+        .memfile("../sw/sweep/sweep.hex")
+    ) mcu (
+        .i_clk(clk_15),
+        .i_rst(!aresetn),
+        .i_GPI_A(GPIO_A),
+        .i_GPI_B(GPIO_B),
+        .i_GPI_C(GPIO_C),
+        .i_GPI_D(GPIO_D),
+        .o_GPO_A(GPIO_A),
+        .o_GPO_B(GPIO_B),
+        .o_GPO_C(GPIO_C),
+        .o_GPO_D(GPIO_D)
+    );
 
 
     wire [15:0] sin_q15;
     wire clk_en;
     nco_q15 #(
-        .CLK_HZ(100_000_000),
-        .FS_HZ(40_000)
+        .CLK_HZ(15_000_000),
+        .FS_HZ(80_000)
     ) nco (
-        .clk    (aclk),
+        .clk    (clk_15),
         .rst_n  (aresetn),
-        .freq_hz(freq),
+        .freq_hz(GPIO_A),
         .sin_q15(sin_q15),
         .cos_q15(),
         .clk_en (clk_en)
     );
 
     reg [5:0] dac_code;
-    always @(posedge aclk) begin
+    always @(posedge clk_15) begin
         dac_code <= q15_to_uq16(sin_q15) >> 10;
     end
     assign r2r = dac_code;

rtl/toplevel/top_serv.v

@@ -1,61 +0,0 @@
-`timescale 1ns/1ps
-
-module top_generic(
-    input wire aclk,
-    input wire aresetn,
-
-    output wire led_green,
-    output wire led_red,
-
-    output wire[5:0] r2r
-);
-
-    wire [31:0] wb_adr;
-    wire [31:0] wb_dat;
-    wire [31:0] wb_rdt;
-    wire [3:0] wb_sel;
-    wire wb_we;
-    wire wb_stb;
-    wire wb_ack;
-
-    wire [31:0] GPIO;
-
-    assign led_green = GPIO[0];
-    assign led_red = GPIO[1];
-    assign r2r = GPIO[8:2];
-
-    serving #(
-        .memfile("../sw/blinky/blinky.hex"),
-        .memsize(8192),
-        .sim(1'b0),
-        .RESET_STRATEGY("MINI"),
-        .WITH_CSR(1)
-    ) serv (
-        .i_clk(aclk),
-        .i_rst(!aresetn),
-        .i_timer_irq(1'b0),
-        .i_wb_rdt(wb_rdt),
-        .i_wb_ack(wb_ack),
-        .o_wb_adr(wb_adr),
-        .o_wb_dat(wb_dat),
-        .o_wb_sel(wb_sel),
-        .o_wb_we(wb_we),
-        .o_wb_stb(wb_stb)
-    );
-
-    wb_gpio #(
-      .address(32'h80000000)
-    ) gpio (
-        .i_wb_clk(aclk),
-        .i_wb_rst(!aresetn),
-        .i_wb_dat(wb_dat),
-        .i_wb_adr(wb_adr),
-        .i_wb_we(wb_we),
-        .i_wb_stb(wb_stb),
-        .i_wb_sel(wb_sel),
-        .o_wb_rdt(wb_rdt),
-        .o_wb_ack(wb_ack),
-        .o_gpio(GPIO)
-    );
-
-endmodule

rtl/util/clog2.vh

@@ -1,10 +1,39 @@
-function integer clog2;
-  input integer value;
-  integer i;
-  begin
-    value = value - 1;
-    for (i = 0; value > 0; i = i + 1)
-      value = value >> 1;
-    clog2 = (i < 1) ? 1 : i;
-  end
-endfunction
+`ifndef CLOG2_VH
+`define CLOG2_VH
+
+// Verilog-2001 compatible ceil(log2(x)) macro (matches $clog2 semantics).
+`define CLOG2(x) \
+  (((x) <= 1) ? 0 : \
+   ((x) <= 2) ? 1 : \
+   ((x) <= 4) ? 2 : \
+   ((x) <= 8) ? 3 : \
+   ((x) <= 16) ? 4 : \
+   ((x) <= 32) ? 5 : \
+   ((x) <= 64) ? 6 : \
+   ((x) <= 128) ? 7 : \
+   ((x) <= 256) ? 8 : \
+   ((x) <= 512) ? 9 : \
+   ((x) <= 1024) ? 10 : \
+   ((x) <= 2048) ? 11 : \
+   ((x) <= 4096) ? 12 : \
+   ((x) <= 8192) ? 13 : \
+   ((x) <= 16384) ? 14 : \
+   ((x) <= 32768) ? 15 : \
+   ((x) <= 65536) ? 16 : \
+   ((x) <= 131072) ? 17 : \
+   ((x) <= 262144) ? 18 : \
+   ((x) <= 524288) ? 19 : \
+   ((x) <= 1048576) ? 20 : \
+   ((x) <= 2097152) ? 21 : \
+   ((x) <= 4194304) ? 22 : \
+   ((x) <= 8388608) ? 23 : \
+   ((x) <= 16777216) ? 24 : \
+   ((x) <= 33554432) ? 25 : \
+   ((x) <= 67108864) ? 26 : \
+   ((x) <= 134217728) ? 27 : \
+   ((x) <= 268435456) ? 28 : \
+   ((x) <= 536870912) ? 29 : \
+   ((x) <= 1073741824) ? 30 : \
+   ((x) <= 2147483648) ? 31 : 32)
+
+`endif

rtl/wb/wb_gpio.v

@@ -8,6 +8,7 @@ module wb_gpio #(
   input  wire [3:0]  i_wb_sel,
   input  wire        i_wb_we,
   input  wire        i_wb_stb,
+  input  wire [31:0] i_gpio,
 
   output reg  [31:0] o_wb_rdt,
   output reg         o_wb_ack,
@@ -34,7 +35,7 @@ module wb_gpio #(
     if (i_wb_rst) begin
       o_wb_rdt <= 32'h0;
     end else if (i_wb_stb && !i_wb_we) begin
-      o_wb_rdt <= o_gpio;
+      o_wb_rdt <= i_gpio;
     end
   end
 
@@ -51,4 +52,4 @@ module wb_gpio #(
     end
   end
 
-endmodule
+endmodule

rtl/wb/wb_gpio_banks.v

@@ -0,0 +1,63 @@
+`default_nettype none
+
+module wb_gpio_banks #(
+  parameter integer NUM_BANKS = 4,
+  parameter [31:0] BASE_ADDR = 32'h8000_0000
+) (
+  input  wire                     i_wb_clk,
+  input  wire                     i_wb_rst,
+  input  wire [31:0]              i_wb_adr,
+  input  wire [31:0]              i_wb_dat,
+  input  wire [3:0]               i_wb_sel,
+  input  wire                     i_wb_we,
+  input  wire                     i_wb_stb,
+  input  wire [NUM_BANKS*32-1:0]  i_gpio,
+  output reg  [31:0]              o_wb_rdt,
+  output reg                      o_wb_ack,
+  output wire [NUM_BANKS*32-1:0]  o_gpio
+);
+
+  wire [NUM_BANKS-1:0]           bank_sel;
+  wire [NUM_BANKS-1:0]           bank_stb;
+  wire [NUM_BANKS*32-1:0]        bank_rdt;
+  wire [NUM_BANKS-1:0]           bank_ack;
+
+  genvar gi;
+  generate
+    for (gi = 0; gi < NUM_BANKS; gi = gi + 1) begin : gen_gpio
+      localparam [31:0] BANK_ADDR = BASE_ADDR + (gi * 4);
+
+      assign bank_sel[gi] = (i_wb_adr == BANK_ADDR);
+      assign bank_stb[gi] = i_wb_stb & bank_sel[gi];
+
+      wb_gpio #(
+        .address(BANK_ADDR)
+      ) u_gpio (
+        .i_wb_clk(i_wb_clk),
+        .i_wb_rst(i_wb_rst),
+        .i_wb_adr(i_wb_adr),
+        .i_wb_dat(i_wb_dat),
+        .i_wb_sel(i_wb_sel),
+        .i_wb_we(i_wb_we),
+        .i_wb_stb(bank_stb[gi]),
+        .i_gpio(i_gpio[gi*32 +: 32]),
+        .o_wb_rdt(bank_rdt[gi*32 +: 32]),
+        .o_wb_ack(bank_ack[gi]),
+        .o_gpio(o_gpio[gi*32 +: 32])
+      );
+    end
+  endgenerate
+
+  integer bi;
+  always @* begin
+    o_wb_rdt = 32'h0000_0000;
+    o_wb_ack = 1'b0;
+    for (bi = 0; bi < NUM_BANKS; bi = bi + 1) begin
+      if (bank_sel[bi]) begin
+        o_wb_rdt = bank_rdt[bi*32 +: 32];
+        o_wb_ack = bank_ack[bi];
+      end
+    end
+  end
+
+endmodule

scripts/hex_to_coe.py

@@ -0,0 +1,136 @@
+#!/usr/bin/env python3
+"""Convert a simple .hex image to Xilinx .coe format.
+
+Supported input:
+- One or more hex tokens per line (e.g. "37" or "0x37")
+- Optional comments after '#' or '//'
+
+By default, each token is written as one .coe entry (8-bit style memory init).
+Use --word-bytes > 1 to pack byte tokens into wider words.
+"""
+
+from __future__ import annotations
+
+import argparse
+from pathlib import Path
+
+
+def parse_tokens(path: Path) -> list[int]:
+    values: list[int] = []
+    for raw in path.read_text().splitlines():
+        line = raw.split("//", 1)[0].split("#", 1)[0].strip()
+        if not line:
+            continue
+        for token in line.replace(",", " ").split():
+            token = token.strip()
+            if not token:
+                continue
+            if token.lower().startswith("0x"):
+                token = token[2:]
+            values.append(int(token, 16))
+    return values
+
+
+def pack_words(
+    byte_values: list[int], word_bytes: int, little_endian: bool
+) -> tuple[list[int], int]:
+    if word_bytes <= 0:
+        raise ValueError("word_bytes must be >= 1")
+    if word_bytes == 1:
+        return byte_values[:], 2
+
+    words: list[int] = []
+    width = word_bytes * 2
+    for i in range(0, len(byte_values), word_bytes):
+        chunk = byte_values[i : i + word_bytes]
+        if len(chunk) < word_bytes:
+            chunk = chunk + [0] * (word_bytes - len(chunk))
+
+        word = 0
+        if little_endian:
+            for b_idx, b in enumerate(chunk):
+                word |= (b & 0xFF) << (8 * b_idx)
+        else:
+            for b in chunk:
+                word = (word << 8) | (b & 0xFF)
+        words.append(word)
+
+    return words, width
+
+
+def main() -> None:
+    parser = argparse.ArgumentParser(description="Convert .hex to Xilinx .coe")
+    parser.add_argument("input_hex", type=Path, help="Input .hex file")
+    parser.add_argument("output_coe", type=Path, help="Output .coe file")
+    parser.add_argument(
+        "--word-bytes",
+        type=int,
+        default=1,
+        help="Bytes per output word (default: 1)",
+    )
+    parser.add_argument(
+        "--little-endian",
+        action="store_true",
+        help="Pack bytes little-endian when --word-bytes > 1 (default)",
+    )
+    parser.add_argument(
+        "--big-endian",
+        action="store_true",
+        help="Pack bytes big-endian when --word-bytes > 1",
+    )
+    parser.add_argument(
+        "--radix",
+        type=int,
+        default=16,
+        choices=[2, 10, 16],
+        help="COE radix (default: 16)",
+    )
+    parser.add_argument(
+        "--depth",
+        type=int,
+        default=0,
+        help="Optional output depth (pads with zeros up to this many words)",
+    )
+    args = parser.parse_args()
+
+    if args.little_endian and args.big_endian:
+        raise SystemExit("Choose only one of --little-endian or --big-endian")
+
+    little_endian = True
+    if args.big_endian:
+        little_endian = False
+
+    byte_values = parse_tokens(args.input_hex)
+    words, hex_digits = pack_words(byte_values, args.word_bytes, little_endian)
+
+    if args.depth > 0 and args.depth < len(words):
+        raise SystemExit(
+            f"Requested --depth={args.depth} but image has {len(words)} words"
+        )
+    if args.depth > len(words):
+        words.extend([0] * (args.depth - len(words)))
+
+    if args.radix == 16:
+        data = [f"{w:0{hex_digits}X}" for w in words]
+    elif args.radix == 10:
+        data = [str(w) for w in words]
+    else:
+        width_bits = args.word_bytes * 8
+        data = [f"{w:0{width_bits}b}" for w in words]
+
+    out_lines = [
+        f"memory_initialization_radix={args.radix};",
+        "memory_initialization_vector=",
+    ]
+    if data:
+        out_lines.extend(
+            [f"{v}," for v in data[:-1]] + [f"{data[-1]};"]
+        )
+    else:
+        out_lines.append("0;")
+
+    args.output_coe.write_text("\n".join(out_lines) + "\n")
+
+
+if __name__ == "__main__":
+    main()

scripts/hex_to_mif.py

@@ -0,0 +1,104 @@
+#!/usr/bin/env python3
+"""Convert a simple .hex image to a plain .mif-style binary file.
+
+Default output format matches build/mem_8kx8b.mif in this repo:
+- one binary word per line
+- no header
+"""
+
+from __future__ import annotations
+
+import argparse
+from pathlib import Path
+
+
+def parse_tokens(path: Path) -> list[int]:
+    values: list[int] = []
+    for raw in path.read_text().splitlines():
+        line = raw.split("//", 1)[0].split("#", 1)[0].strip()
+        if not line:
+            continue
+        for token in line.replace(",", " ").split():
+            if token.lower().startswith("0x"):
+                token = token[2:]
+            values.append(int(token, 16))
+    return values
+
+
+def pack_words(
+    byte_values: list[int], word_bytes: int, little_endian: bool
+) -> list[int]:
+    if word_bytes <= 0:
+        raise ValueError("word_bytes must be >= 1")
+    if word_bytes == 1:
+        return byte_values[:]
+
+    words: list[int] = []
+    for i in range(0, len(byte_values), word_bytes):
+        chunk = byte_values[i : i + word_bytes]
+        if len(chunk) < word_bytes:
+            chunk = chunk + [0] * (word_bytes - len(chunk))
+
+        word = 0
+        if little_endian:
+            for b_idx, b in enumerate(chunk):
+                word |= (b & 0xFF) << (8 * b_idx)
+        else:
+            for b in chunk:
+                word = (word << 8) | (b & 0xFF)
+        words.append(word)
+    return words
+
+
+def main() -> None:
+    parser = argparse.ArgumentParser(description="Convert .hex to plain .mif")
+    parser.add_argument("input_hex", type=Path, help="Input .hex file")
+    parser.add_argument("output_mif", type=Path, help="Output .mif file")
+    parser.add_argument(
+        "--word-bytes",
+        type=int,
+        default=1,
+        help="Bytes per output word (default: 1)",
+    )
+    parser.add_argument(
+        "--little-endian",
+        action="store_true",
+        help="Pack bytes little-endian when --word-bytes > 1 (default)",
+    )
+    parser.add_argument(
+        "--big-endian",
+        action="store_true",
+        help="Pack bytes big-endian when --word-bytes > 1",
+    )
+    parser.add_argument(
+        "--depth",
+        type=int,
+        default=0,
+        help="Optional output depth (pads with zeros up to this many words)",
+    )
+    args = parser.parse_args()
+
+    if args.little_endian and args.big_endian:
+        raise SystemExit("Choose only one of --little-endian or --big-endian")
+
+    little_endian = True
+    if args.big_endian:
+        little_endian = False
+
+    words = pack_words(parse_tokens(args.input_hex), args.word_bytes, little_endian)
+    width_bits = args.word_bytes * 8
+    max_word = (1 << width_bits) - 1
+
+    if args.depth > 0 and args.depth < len(words):
+        raise SystemExit(
+            f"Requested --depth={args.depth} but image has {len(words)} words"
+        )
+    if args.depth > len(words):
+        words.extend([0] * (args.depth - len(words)))
+
+    lines = [f"{(w & max_word):0{width_bits}b}" for w in words]
+    args.output_mif.write_text("\n".join(lines) + ("\n" if lines else ""))
+
+
+if __name__ == "__main__":
+    main()

scripts/jtag_write_ram.py

@@ -0,0 +1,196 @@
+#!/usr/bin/env python3
+"""Write a file into serving_ram_jtag over Spartan-6 USER JTAG via OpenOCD.
+
+This script targets the protocol implemented by rtl/serv/serving_ram_jtag_bridge.v:
+  frame bit[0]            = write_enable
+  frame bit[32:1]         = 32-bit address
+  frame bit[40:33]        = data byte
+
+Notes:
+- Frame is shifted LSB-first (OpenOCD drscan integer value format matches this).
+- USER1/USER2 opcode selection is Spartan-6 specific (IR opcodes 0x02/0x03, IR length 6).
+"""
+
+from __future__ import annotations
+
+import argparse
+import pathlib
+import re
+import subprocess
+import sys
+import tempfile
+from typing import Dict, List, Tuple
+
+JTAG_ADDR_W = 32
+JTAG_FRAME_W = 1 + JTAG_ADDR_W + 8
+
+
+def parse_args() -> argparse.Namespace:
+    p = argparse.ArgumentParser(description="Write file to serving RAM over JTAG")
+    p.add_argument("input", help="Input file (.bin or readmemh-style .hex/.mem)")
+    p.add_argument(
+        "--ram-addr-width",
+        "--addr-width",
+        dest="ram_addr_width",
+        type=int,
+        default=8,
+        help="RAM address width (aw) in HDL, default: 8",
+    )
+    p.add_argument("--base-addr", type=lambda x: int(x, 0), default=0, help="Base address for .bin input")
+    p.add_argument("--tap", default="xc6s.tap", help="OpenOCD tap name (default: xc6s.tap)")
+    p.add_argument(
+        "--user-chain",
+        type=int,
+        choices=[1, 2],
+        default=1,
+        help="BSCAN user chain used in HDL (default: 1)",
+    )
+    p.add_argument("--openocd-cfg", action="append", default=[], help="OpenOCD -f config file (repeatable)")
+    p.add_argument("--openocd-cmd", action="append", default=[], help="Extra OpenOCD -c command before programming")
+    p.add_argument("--limit", type=int, default=None, help="Write only first N bytes")
+    p.add_argument("--dry-run", action="store_true", help="Generate and print TCL only")
+    return p.parse_args()
+
+
+def _strip_line_comments(line: str) -> str:
+    return line.split("//", 1)[0]
+
+
+def parse_readmemh_text(path: pathlib.Path) -> Dict[int, int]:
+    """Parse a simple readmemh-style file with optional @address directives."""
+    text = path.read_text(encoding="utf-8")
+    words: Dict[int, int] = {}
+    addr = 0
+
+    for raw_line in text.splitlines():
+        line = _strip_line_comments(raw_line).strip()
+        if not line:
+            continue
+        for tok in line.split():
+            tok = tok.strip()
+            if not tok:
+                continue
+            if tok.startswith("@"):
+                addr = int(tok[1:], 16)
+                continue
+            if not re.fullmatch(r"[0-9a-fA-F]+", tok):
+                raise ValueError(f"Unsupported token '{tok}' in {path}")
+            val = int(tok, 16)
+            if val < 0 or val > 0xFF:
+                raise ValueError(f"Byte value out of range at address 0x{addr:x}: {tok}")
+            words[addr] = val
+            addr += 1
+
+    return words
+
+
+def load_image(path: pathlib.Path, base_addr: int) -> List[Tuple[int, int]]:
+    suffix = path.suffix.lower()
+    if suffix == ".bin":
+        blob = path.read_bytes()
+        return [(base_addr + i, b) for i, b in enumerate(blob)]
+    if suffix in {".hex", ".mem", ".vmem"}:
+        words = parse_readmemh_text(path)
+        return sorted(words.items())
+    raise ValueError("Unsupported input format. Use .bin, .hex, .mem, or .vmem")
+
+
+def build_write_frame(addr: int, data: int) -> int:
+    return (data << (JTAG_ADDR_W + 1)) | ((addr & ((1 << JTAG_ADDR_W) - 1)) << 1) | 0x1
+
+
+def build_openocd_tcl(entries: List[Tuple[int, int]], tap: str, user_chain: int, pre_cmds: List[str]) -> str:
+    ir_opcode = 0x02 if user_chain == 1 else 0x03
+
+    lines: List[str] = []
+    lines.append("init")
+    for cmd in pre_cmds:
+        lines.append(cmd)
+    lines.append(f"irscan {tap} 0x{ir_opcode:x} -endstate IDLE")
+
+    for addr, data in entries:
+        frame = build_write_frame(addr, data)
+        lines.append(f"drscan {tap} {JTAG_FRAME_W} 0x{frame:x} -endstate IDLE")
+
+    lines.append("shutdown")
+    lines.append("")
+    return "\n".join(lines)
+
+
+def run_openocd(cfg_files: List[str], script_path: pathlib.Path) -> int:
+    cmd = ["openocd"]
+    for cfg in cfg_files:
+        cmd += ["-f", cfg]
+    cmd += ["-f", str(script_path)]
+
+    proc = subprocess.run(cmd)
+    return proc.returncode
+
+
+def main() -> int:
+    args = parse_args()
+    in_path = pathlib.Path(args.input)
+
+    if not in_path.exists():
+        print(f"error: input file not found: {in_path}", file=sys.stderr)
+        return 2
+
+    entries = load_image(in_path, args.base_addr)
+    if args.limit is not None:
+        entries = entries[: args.limit]
+
+    if not entries:
+        print("error: no bytes found to write", file=sys.stderr)
+        return 2
+
+    if args.ram_addr_width < 1 or args.ram_addr_width > JTAG_ADDR_W:
+        print(
+            f"error: --ram-addr-width must be in [1, {JTAG_ADDR_W}] for this protocol",
+            file=sys.stderr,
+        )
+        return 2
+
+    max_jtag_addr = (1 << JTAG_ADDR_W) - 1
+    max_addr = (1 << args.ram_addr_width) - 1
+    for addr, _ in entries:
+        if addr < 0 or addr > max_jtag_addr:
+            print(
+                f"error: address 0x{addr:x} exceeds 32-bit protocol range (max 0x{max_jtag_addr:x})",
+                file=sys.stderr,
+            )
+            return 2
+        if addr > max_addr:
+            print(
+                f"error: address 0x{addr:x} exceeds RAM addr width {args.ram_addr_width} (max 0x{max_addr:x})",
+                file=sys.stderr,
+            )
+            return 2
+
+    tcl = build_openocd_tcl(entries, args.tap, args.user_chain, args.openocd_cmd)
+
+    if args.dry_run:
+        print(tcl, end="")
+        print(f"# bytes: {len(entries)}", file=sys.stderr)
+        return 0
+
+    if not args.openocd_cfg:
+        print("error: provide at least one --openocd-cfg unless using --dry-run", file=sys.stderr)
+        return 2
+
+    with tempfile.NamedTemporaryFile("w", suffix=".tcl", delete=False) as tf:
+        tf.write(tcl)
+        tcl_path = pathlib.Path(tf.name)
+
+    print(f"Programming {len(entries)} bytes via JTAG...")
+    rc = run_openocd(args.openocd_cfg, tcl_path)
+    if rc != 0:
+        print(f"error: openocd failed with exit code {rc}", file=sys.stderr)
+        print(f"TCL kept at: {tcl_path}", file=sys.stderr)
+        return rc
+
+    print("Done.")
+    return 0
+
+
+if __name__ == "__main__":
+    raise SystemExit(main())

scripts/planahead.sh

@@ -1,4 +1,5 @@
 #!/bin/bash
 cd build
-. /opt/packages/xilinx/ISE/14.7/ISE_DS/settings64.sh
-planAhead -mode gui -source ../scripts/planahead.tcl 
+. /opt/Xilinx/14.7/ISE_DS/settings64.sh
+Xephyr :1 -screen 1600x900 &
+DISPLAY=:1 planAhead -mode batch -source ../scripts/planahead.tcl 

scripts/planahead.tcl

@@ -4,4 +4,5 @@ add_files -norecurse ../out/synth/synth.ngc
 import_files -force -norecurse
 import_files -fileset constrs_1 -force -norecurse ../boards/mimas_v1/constraints.ucf
 import_as_run -run impl_1 -twx ../out/synth/timing.twx ../out/synth/synth.ncd
-open_run impl_1
+open_run impl_1
+start_gui

sim/overrides/serving_ram.v

@@ -1,51 +0,0 @@
-/* serving_ram.v : I/D SRAM for the serving SoC
- *
- * ISC License
- *
- * Copyright (C) 2020 Olof Kindgren <olof.kindgren@gmail.com>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-`default_nettype none
-module serving_ram
-  #(//Memory parameters
-    parameter depth = 256,
-    parameter aw    = $clog2(depth),
-    parameter memfile = "")
-   (input wire		i_clk,
-    input wire [aw-1:0]	i_waddr,
-    input wire [7:0]	i_wdata,
-    input wire		i_wen,
-    input wire [aw-1:0]	i_raddr,
-    output reg [7:0]	o_rdata);
-
-   reg [7:0]		mem [0:depth-1] /* verilator public */;
-
-   always @(posedge i_clk) begin
-      if (i_wen) mem[i_waddr]   <= i_wdata;
-      o_rdata <= mem[i_raddr];
-   end
-   
-   integer i;
-initial begin
-  // Fill unused/uninitialized memory with a predefined value
-  for (i = 0; i < depth; i = i + 1)
-    mem[i] = 8'h00;   // <- pick your fill value (00, FF, etc.)
-
-  if (|memfile) begin
-    $display("Preloading %m from %s", memfile);
-    $readmemh(memfile, mem);
-  end
-end
-endmodule

sim/tb/tb_serving.v

@@ -33,7 +33,7 @@ module tb_serving();
     serving #(
         .memfile("../sw/blinky/blinky.hex"),
         .memsize(8192),
-        .sim(1'b0),
+        .sim(1'b1),
         .RESET_STRATEGY("MINI"),
         .WITH_CSR(1)
     ) serv (
@@ -50,7 +50,7 @@ module tb_serving();
     );
 
     wb_gpio #(
-      .address(32'h80000000)
+      .address(32'h40000000)
     ) gpio (
         .i_wb_clk(clk),
         .i_wb_dat(wb_dat),
@@ -58,9 +58,10 @@ module tb_serving();
         .i_wb_we(wb_we),
         .i_wb_stb(wb_stb),
         .i_wb_sel(wb_sel),
+        .i_gpio(GPIO),
         .o_wb_rdt(wb_rdt),
         .o_wb_ack(wb_ack),
         .o_gpio(GPIO)
     );
 
-endmodule
+endmodule

sw/.gitignore

@@ -0,0 +1,8 @@
+*.o
+*.hex
+*.bin
+*.map
+*.elf.asm
+*.elf
+*.coe
+*.mif

sw/blinky/Makefile

@@ -1,14 +1,56 @@
-TOOLCHAIN_PREFIX?=riscv64-elf-
-CC=$(TOOLCHAIN_PREFIX)gcc
-OBJCOPY=$(TOOLCHAIN_PREFIX)objcopy
+TOOLCHAIN_PREFIX ?= riscv64-elf-
 
-%.elf: %.S link.ld
-# 	$(CC) -nostartfiles -nostdlib -march=rv32i_zicsr -mabi=ilp32 -Tlink.ld -o$@ $<
-	$(CC) -nostartfiles -nostdlib -ffreestanding -march=rv32i_zicsr -mabi=ilp32 -Tlink.ld -o$@ $<
-%.bin: %.elf
+CC      := $(TOOLCHAIN_PREFIX)gcc
+OBJCOPY := $(TOOLCHAIN_PREFIX)objcopy
+OBJDUMP := $(TOOLCHAIN_PREFIX)objdump
+SIZE    := $(TOOLCHAIN_PREFIX)size
+
+TARGET  := blinky
+SRCS_C  := blinky.c
+SRCS_S  := start.s
+OBJS    := $(SRCS_C:.c=.o) $(SRCS_S:.s=.o)
+
+ARCH_FLAGS := -march=rv32i_zicsr -mabi=ilp32
+CFLAGS     := $(ARCH_FLAGS) -Os -ffreestanding -fno-builtin -Wall -Wextra
+ASFLAGS    := $(ARCH_FLAGS)
+LDFLAGS    := $(ARCH_FLAGS) -nostdlib -nostartfiles -Wl,-Bstatic,-Tlink.ld,--gc-sections,-Map,$(TARGET).map
+
+HEX_TO_COE := ../../scripts/hex_to_coe.py
+HEX_TO_MIF := ../../scripts/hex_to_mif.py
+
+.PHONY: all clean disasm size
+
+all: $(TARGET).elf $(TARGET).bin $(TARGET).hex $(TARGET).coe $(TARGET).mif $(TARGET).elf.asm
+
+$(TARGET).elf: $(OBJS) link.ld
+	$(CC) $(LDFLAGS) -o $@ $(OBJS)
+
+%.o: %.c
+	$(CC) $(CFLAGS) -c -o $@ $<
+
+%.o: %.s
+	$(CC) $(ASFLAGS) -c -o $@ $<
+
+$(TARGET).bin: $(TARGET).elf
 	$(OBJCOPY) -O binary $< $@
-%.hex: %.bin
+
+$(TARGET).hex: $(TARGET).bin
 	hexdump -v -e '1/1 "%02x\n"' $< > $@
 
+$(TARGET).coe: $(TARGET).hex
+	$(HEX_TO_COE) $< $@
+
+$(TARGET).mif: $(TARGET).hex
+	$(HEX_TO_MIF) $< $@
+
+$(TARGET).elf.asm: $(TARGET).elf
+	$(OBJDUMP) -d -S $< > $@
+
+disasm: $(TARGET).elf.asm
+
+size: $(TARGET).elf
+	$(SIZE) $<
+
 clean:
-	rm -f *.elf *.bin *.hex
+	rm -f $(TARGET).elf $(TARGET).bin $(TARGET).hex $(TARGET).coe $(TARGET).mif \
+		$(TARGET).elf.asm $(TARGET).map $(OBJS)

sw/blinky/blinky.S

@@ -1,17 +0,0 @@
-#define GPIO_BASE 0x80000000
-#define DELAY 2
-
-.globl _start
-_start:
-	lui a0, %hi(GPIO_BASE)
-	addi a0, a0, %lo(GPIO_BASE)
-	addi t0, zero, 0
-	li t1, DELAY
-.lp1:
-	sb t0, 0(a0)
-	addi t0, t0, 1
-	and t2, zero, zero
-time1:
-	addi t2, t2, 1
-	bne t1, t2, time1
-	j .lp1

sw/blinky/blinky.c

@@ -0,0 +1,27 @@
+#include <stdint.h>
+
+#define GPIO_BASE 0x40000000u
+#define VOUT_BASE 0x40000004u
+
+static volatile uint32_t * const gpio = (volatile uint32_t *)GPIO_BASE;
+static volatile uint32_t * const vout = (volatile uint32_t *)VOUT_BASE;
+
+static void delay(volatile uint32_t ticks){
+    while (ticks--) {
+        __asm__ volatile ("nop");
+    }
+}
+
+int main(void)
+{
+    uint32_t v = 0;
+
+    for (;;) {
+        for(int i=0; i<1000; i++){
+            *vout = v;
+            v++;
+            delay(5u);
+        }
+        *gpio ^= 0xffffffff;
+    }
+}

sw/blinky/blinky.hex

@@ -1,40 +0,0 @@
-37
-05
-00
-80
-13
-05
-05
-00
-93
-02
-00
-00
-13
-03
-20
-00
-23
-00
-55
-00
-93
-82
-12
-00
-b3
-73
-00
-00
-93
-83
-13
-00
-e3
-1e
-73
-fe
-6f
-f0
-df
-fe

sw/blinky/link.ld

@@ -1,10 +1,33 @@
-OUTPUT_ARCH( "riscv" )
+OUTPUT_ARCH("riscv")
 ENTRY(_start)
 
+MEMORY
+{
+  RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 8K
+}
+
 SECTIONS
 {
-  . = 0x00000000;
-  .text : { *(.text) }
-  .data : { *(.data) }
-  .bss : { *(.bss) }
+  .text :
+  {
+    KEEP(*(.text.init))
+    *(.text .text.*)
+    *(.rodata .rodata.*)
+  } > RAM
+
+  .data :
+  {
+    *(.data .data.*)
+  } > RAM
+
+  .bss (NOLOAD) :
+  {
+    __bss_start = .;
+    *(.bss .bss.*)
+    *(COMMON)
+    __bss_end = .;
+  } > RAM
+
+  . = ALIGN(4);
+  __stack_top = ORIGIN(RAM) + LENGTH(RAM);
 }

sw/blinky/start.s

@@ -0,0 +1,23 @@
+.section .text.init
+.globl _start
+.type _start, @function
+
+_start:
+    la sp, __stack_top
+
+    # Zero .bss
+    la t0, __bss_start
+    la t1, __bss_end
+1:
+    bgeu t0, t1, 2f
+    sw zero, 0(t0)
+    addi t0, t0, 4
+    j 1b
+
+2:
+    call main
+
+3:
+    j 3b
+
+.size _start, .-_start

sw/sweep/Makefile

@@ -0,0 +1,56 @@
+TOOLCHAIN_PREFIX ?= riscv64-elf-
+
+CC      := $(TOOLCHAIN_PREFIX)gcc
+OBJCOPY := $(TOOLCHAIN_PREFIX)objcopy
+OBJDUMP := $(TOOLCHAIN_PREFIX)objdump
+SIZE    := $(TOOLCHAIN_PREFIX)size
+
+TARGET  := sweep
+SRCS_C  := sweep.c
+SRCS_S  := start.s
+OBJS    := $(SRCS_C:.c=.o) $(SRCS_S:.s=.o)
+
+ARCH_FLAGS := -march=rv32i_zicsr -mabi=ilp32
+CFLAGS     := $(ARCH_FLAGS) -Os -ffreestanding -fno-builtin -Wall -Wextra
+ASFLAGS    := $(ARCH_FLAGS)
+LDFLAGS    := $(ARCH_FLAGS) -nostdlib -nostartfiles -Wl,-Bstatic,-Tlink.ld,--gc-sections,-Map,$(TARGET).map
+
+HEX_TO_COE := ../../scripts/hex_to_coe.py
+HEX_TO_MIF := ../../scripts/hex_to_mif.py
+
+.PHONY: all clean disasm size
+
+all: $(TARGET).elf $(TARGET).bin $(TARGET).hex $(TARGET).coe $(TARGET).mif $(TARGET).elf.asm
+
+$(TARGET).elf: $(OBJS) link.ld
+	$(CC) $(LDFLAGS) -o $@ $(OBJS)
+
+%.o: %.c
+	$(CC) $(CFLAGS) -c -o $@ $<
+
+%.o: %.s
+	$(CC) $(ASFLAGS) -c -o $@ $<
+
+$(TARGET).bin: $(TARGET).elf
+	$(OBJCOPY) -O binary $< $@
+
+$(TARGET).hex: $(TARGET).bin
+	hexdump -v -e '1/1 "%02x\n"' $< > $@
+
+$(TARGET).coe: $(TARGET).hex
+	$(HEX_TO_COE) $< $@
+
+$(TARGET).mif: $(TARGET).hex
+	$(HEX_TO_MIF) $< $@
+
+$(TARGET).elf.asm: $(TARGET).elf
+	$(OBJDUMP) -d -S $< > $@
+
+disasm: $(TARGET).elf.asm
+
+size: $(TARGET).elf
+	$(SIZE) $<
+
+clean:
+	rm -f $(TARGET).elf $(TARGET).bin $(TARGET).hex $(TARGET).coe $(TARGET).mif \
+		$(TARGET).elf.asm $(TARGET).map $(OBJS)

sw/sweep/link.ld

@@ -0,0 +1,33 @@
+OUTPUT_ARCH("riscv")
+ENTRY(_start)
+
+MEMORY
+{
+  RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 8K
+}
+
+SECTIONS
+{
+  .text :
+  {
+    KEEP(*(.text.init))
+    *(.text .text.*)
+    *(.rodata .rodata.*)
+  } > RAM
+
+  .data :
+  {
+    *(.data .data.*)
+  } > RAM
+
+  .bss (NOLOAD) :
+  {
+    __bss_start = .;
+    *(.bss .bss.*)
+    *(COMMON)
+    __bss_end = .;
+  } > RAM
+
+  . = ALIGN(4);
+  __stack_top = ORIGIN(RAM) + LENGTH(RAM);
+}

sw/sweep/start.s

@@ -0,0 +1,23 @@
+.section .text.init
+.globl _start
+.type _start, @function
+
+_start:
+    la sp, __stack_top
+
+    # Zero .bss
+    la t0, __bss_start
+    la t1, __bss_end
+1:
+    bgeu t0, t1, 2f
+    sw zero, 0(t0)
+    addi t0, t0, 4
+    j 1b
+
+2:
+    call main
+
+3:
+    j 3b
+
+.size _start, .-_start

sw/sweep/sweep.c

@@ -0,0 +1,14 @@
+#include <stdint.h>
+
+#define GPIO_BASE 0x40000000u
+
+static volatile uint32_t * const R_FREQ = (volatile uint32_t *)GPIO_BASE;
+
+void main(){
+    for(;;){
+        for(int i=1000; i<10000; i++){
+            *R_FREQ = i;
+            for(int j=0; j<100; j++) asm volatile("nop");
+        }
+    }
+}