 Joppe Blondel
|
d557e6812d
|
Added xsim postsimulation
Signed-off-by: Joppe Blondel <joppe@blondel.nl>
|
2022-09-05 18:40:03 +02:00 |
|
|
Joppe Blondel
|
1717eba787
|
Start with xsim
Signed-off-by: Joppe Blondel <joppe@blondel.nl>
|
2022-09-05 16:04:37 +02:00 |
|
|
Joppe Blondel
|
c1b3d252ff
|
Vivado output generation
Signed-off-by: Joppe Blondel <joppe@blondel.nl>
|
2022-09-05 15:27:41 +02:00 |
|
|
Joppe Blondel
|
b8267303a2
|
Added vivado synth
Signed-off-by: Joppe Blondel <joppe@blondel.nl>
|
2022-09-05 15:08:27 +02:00 |
|
|
Joppe Blondel
|
15d072bbb7
|
Added vivado IP generatioon
Signed-off-by: Joppe Blondel <joppe@blondel.nl>
|
2022-09-05 14:44:09 +02:00 |
|
|
Joppe Blondel
|
1bf61807fc
|
ISE coregen added
Signed-off-by: Joppe Blondel <joppe@blondel.nl>
|
2022-09-05 13:55:03 +02:00 |
|
|
Joppe Blondel
|
aa9aa6aa78
|
Fixed rmserver/rmbuild bug
Signed-off-by: Joppe Blondel <joppe@blondel.nl>
|
2022-09-05 13:18:57 +02:00 |
|
|
Joppe Blondel
|
0e95f91fb2
|
Added isim target
Signed-off-by: Joppe Blondel <joppe@blondel.nl>
|
2022-09-05 13:11:32 +02:00 |
|
|
Joppe Blondel
|
96a406b2eb
|
Full bit and timing log generation
Signed-off-by: Joppe Blondel <joppe@blondel.nl>
|
2022-09-05 12:38:21 +02:00 |
|
|
Joppe Blondel
|
7aa7fd59b0
|
Moved to more fusesoc like build style
Signed-off-by: Joppe Blondel <joppe@blondel.nl>
|
2022-09-05 12:23:55 +02:00 |
|
|
Joppe Blondel
|
dc97a7d5a8
|
Added impl
Signed-off-by: Joppe Blondel <joppe@blondel.nl>
|
2022-09-04 19:48:46 +02:00 |
|
|
Jojojoppe
|
162aaf47a0
|
New project structure
Rewrite of all functions
Signed-off-by: Jojojoppe <joppe@blondel.nl>
|
2022-09-03 21:52:29 +02:00 |
|
|
Joppe Blondel
|
cbcea361bb
|
Added basic zynq setup
Signed-off-by: Joppe Blondel <joppe@blondel.nl>
|
2022-09-03 17:11:47 +02:00 |
|
|
Joppe Blondel
|
bf883f3355
|
Added readme text
Signed-off-by: Joppe Blondel <joppe@blondel.nl>
|
2022-09-03 15:42:55 +02:00 |
|
|
Joppe Blondel
|
af52ee65fa
|
Added spartan 6 example
Signed-off-by: Joppe Blondel <joppe@blondel.nl>
|
2022-09-03 15:40:43 +02:00 |
|