Start with xsim

Signed-off-by: Joppe Blondel <joppe@blondel.nl>

examples/zynq7000/SIM/tb_heartbeat.vhd

@@ -0,0 +1,44 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity tb_heartbeat is
+end entity;
+
+architecture behavioural of tb_heartbeat is
+    -- COMPONENTS
+    -- ----------
+    component heartbeat is
+        generic (
+            Fin  : integer := 100000000;
+            Fout : integer := 8
+        );
+        port (
+            ACLK    : in std_logic;
+            ARESETN : in std_logic;
+            LED     : out std_logic_vector(1 downto 0)
+        );
+    end component;
+    -- SIGNALS
+    -- -------
+    signal ACLK : std_logic := '0';
+    signal LED : std_logic_vector(1 downto 0) := "00";
+    signal ARESETN : std_logic := '0';
+begin
+    c_heartbeat : component heartbeat generic map(
+        50000000,
+        5000000
+        ) port map(
+        ACLK    => ACLK,
+        ARESETN => ARESETN,
+        LED     => LED
+    );
+    ACLK <= not ACLK after 10 ns;
+    ARESETN <= '1' after 150 ns;
+
+    process
+    begin
+        wait for 5000 ns;
+        report "END OF SIMULATION" severity failure;
+    end process;
+end architecture;

examples/zynq7000/project.cfg

@@ -39,7 +39,7 @@ package             = clg400
 speedgrade          = -2
 toplevel            = toplevel
 # Created netlist toplevel
-netlist_top         = toplevel
+netlist_top         = toplevel.heartbeat_i
 synth_opts          = -flatten_hierarchy none -keep_equivalent_registers
 #opt_opts           =
 #place_opts         =
@@ -51,4 +51,23 @@ files_vhdl          = RTL/heartbeat.vhd RTL/toplevel.vhd
 #files_sysverilog   =
 files_con           = CON/toplevel.xdc
 files_xci           = OUT/ip/rst_gen/rst_gen.xci OUT/ip/zynqps/zynqps.xci
+# ######################################
+
+# ######################################
+# Behavioural simulation
+[target.sim]
+toolchain           = xsim
+
+# Toolchain settings
+toplevel            = tb_heartbeat
+vcdlevels           = 20
+runtime             = all
+#xelab_opts         = 
+
+# Fileset
+files_vhdl          = RTL/heartbeat.vhd
+                      SIM/tb_heartbeat.vhd
+#files_verilog      =
+#files_sysverilog   =
+#files_xci          = 
 # ######################################