Full bit and timing log generation

Signed-off-by: Joppe Blondel <joppe@blondel.nl>
2022-09-05 12:38:21 +02:00
parent 7aa7fd59b0
commit 96a406b2eb
4 changed files with 88 additions and 0 deletions
--- a/examples/spartan6/project.cfg
+++ b/examples/spartan6/project.cfg
@ -23,6 +23,9 @@ toplevel            = toplevel
 #ngdbuild_opts      =
 #map_opts           =
 #par_opts           =
+#netgen_opts        =
+#bitgen_opts        =
+#trce_opts          =

 # Fileset
 files_vhdl          = RTL/toplevel.vhd