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1717eba787
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Start with xsim
Signed-off-by: Joppe Blondel <joppe@blondel.nl>
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2022-09-05 16:04:37 +02:00 |
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c1b3d252ff
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Vivado output generation
Signed-off-by: Joppe Blondel <joppe@blondel.nl>
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2022-09-05 15:27:41 +02:00 |
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b8267303a2
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Added vivado synth
Signed-off-by: Joppe Blondel <joppe@blondel.nl>
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2022-09-05 15:08:27 +02:00 |
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15d072bbb7
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Added vivado IP generatioon
Signed-off-by: Joppe Blondel <joppe@blondel.nl>
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2022-09-05 14:44:09 +02:00 |
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1bf61807fc
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ISE coregen added
Signed-off-by: Joppe Blondel <joppe@blondel.nl>
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2022-09-05 13:55:03 +02:00 |
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aa9aa6aa78
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Fixed rmserver/rmbuild bug
Signed-off-by: Joppe Blondel <joppe@blondel.nl>
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2022-09-05 13:18:57 +02:00 |
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0e95f91fb2
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Added isim target
Signed-off-by: Joppe Blondel <joppe@blondel.nl>
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2022-09-05 13:11:32 +02:00 |
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96a406b2eb
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Full bit and timing log generation
Signed-off-by: Joppe Blondel <joppe@blondel.nl>
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2022-09-05 12:38:21 +02:00 |
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7aa7fd59b0
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Moved to more fusesoc like build style
Signed-off-by: Joppe Blondel <joppe@blondel.nl>
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2022-09-05 12:23:55 +02:00 |
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dc97a7d5a8
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Added impl
Signed-off-by: Joppe Blondel <joppe@blondel.nl>
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2022-09-04 19:48:46 +02:00 |
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162aaf47a0
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New project structure
Rewrite of all functions
Signed-off-by: Jojojoppe <joppe@blondel.nl>
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2022-09-03 21:52:29 +02:00 |
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cbcea361bb
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Added basic zynq setup
Signed-off-by: Joppe Blondel <joppe@blondel.nl>
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2022-09-03 17:11:47 +02:00 |
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bf883f3355
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Added readme text
Signed-off-by: Joppe Blondel <joppe@blondel.nl>
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2022-09-03 15:42:55 +02:00 |
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af52ee65fa
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Added spartan 6 example
Signed-off-by: Joppe Blondel <joppe@blondel.nl>
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2022-09-03 15:40:43 +02:00 |
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