43 lines
1.2 KiB
Verilog
43 lines
1.2 KiB
Verilog
`timescale 1ns/1ps
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module sampling(
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input wire adc_A,
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input wire adc_B,
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output wire adc_O,
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input wire clk,
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input wire reset_n
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);
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wire sigmadelta_sample;
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sigmadelta_sampler m_sdsampler(
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.clk(clk),
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.A(adc_A),
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.B(adc_B),
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.out(sigmadelta_sample)
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);
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assign adc_O = sigmadelta_sample;
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// RC model, output is y_next_q15
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// ------------------------------
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reg signed [15:0] y_q15;
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wire signed [15:0] x_q15 = sigmadelta_sample ? 16'sh7fff : 16'sh0000;
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wire signed [15:0] e_q15 = x_q15 - y_q15;
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wire signed [31:0] prod_q30 = $signed(16'sh0b00) * $signed(e_q15); // factor should be 0b3b, used bit simplified here
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wire signed [15:0] delta_q15 = prod_q30 >>> 15;
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wire signed [15:0] y_next_q15 = y_q15 + delta_q15;
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// Optional clamp to [0, 0x7FFF] (keeps GTKWave tidy)
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function signed [15:0] clamp01_q15(input signed [15:0] v);
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if (v < 16'sd0000) clamp01_q15 = 16'sd0000;
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else if (v > 16'sh7FFF) clamp01_q15 = 16'sh7FFF;
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else clamp01_q15 = v;
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endfunction
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) y_q15 <= 16'sd0000;
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else y_q15 <= clamp01_q15(y_next_q15);
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end
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// ------------------------------
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endmodule |