`timescale 1ns/1ps

module sampling(
    input wire adc_A,
    input wire adc_B,
    output wire adc_O,

    input wire clk,
    input wire reset_n
);
    wire sigmadelta_sample;

    sigmadelta_sampler m_sdsampler(
      .clk(clk),
      .A(adc_A),
      .B(adc_B),
      .out(sigmadelta_sample)
    );
    assign adc_O = sigmadelta_sample;

    // RC model, output is y_next_q15
    // ------------------------------
    reg signed [15:0] y_q15;
    wire signed [15:0] x_q15 = sigmadelta_sample ? 16'sh7fff : 16'sh0000;
    wire signed [15:0] e_q15 = x_q15 - y_q15;
    wire signed [31:0] prod_q30 = $signed(16'sh0b00) * $signed(e_q15); // factor should be 0b3b, used bit simplified here
    wire signed [15:0] delta_q15 = prod_q30 >>> 15;
    wire signed [15:0] y_next_q15 = y_q15 + delta_q15;

    // Optional clamp to [0, 0x7FFF] (keeps GTKWave tidy)
    function signed [15:0] clamp01_q15(input signed [15:0] v);
        if (v < 16'sd0000) clamp01_q15 = 16'sd0000;
        else if (v > 16'sh7FFF) clamp01_q15 = 16'sh7FFF;
        else clamp01_q15 = v;
    endfunction

    always @(posedge clk or negedge reset_n) begin
        if (!reset_n) y_q15 <= 16'sd0000;
        else y_q15 <= clamp01_q15(y_next_q15);
    end
    // ------------------------------

endmodule