39 lines
718 B
Verilog
39 lines
718 B
Verilog
`timescale 1ns/1ps
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module tb_sigmadelta();
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// Clock and reset generation
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reg clk;
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reg resetn;
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initial clk <= 1'b0;
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initial resetn <= 1'b0;
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always #6.667 clk <= !clk;
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initial #40 resetn <= 1'b1;
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// Default run
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initial begin
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$dumpfile("out.vcd");
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$dumpvars;
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#1_000_000
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$finish;
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end;
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wire sd_a;
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wire sd_b;
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wire sd_o;
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// 3K3R 220PC 15MHZT
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sigmadelta_sampler sd_sampler(
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.clk(clk),
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.a(sd_a), .b(sd_b),
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.o(sd_o)
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);
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wire signed [15:0] sample_q15;
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sigmadelta_rcmodel_q15 rc_model(
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.clk(clk), .resetn(resetn),
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.sd_sample(sd_o),
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.sample_q15(sample_q15)
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);
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endmodule
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