`timescale 1ns/1ps

module tb_sigmadelta();
    // Clock and reset generation
    reg clk;
    reg resetn;
    initial clk <= 1'b0;
    initial resetn <= 1'b0;
    always #6.667 clk <= !clk;
    initial #40 resetn <= 1'b1;

    // Default run
    initial begin
        $dumpfile("out.vcd");
        $dumpvars;
        #1_000_000
        $finish;
    end;

    wire sd_a;
    wire sd_b;
    wire sd_o;
    // 3K3R 220PC 15MHZT
    sigmadelta_sampler sd_sampler(
        .clk(clk),
        .a(sd_a), .b(sd_b),
        .o(sd_o)
    );


    wire signed [15:0] sample_q15;
    sigmadelta_rcmodel_q15 rc_model(
        .clk(clk), .resetn(resetn),
        .sd_sample(sd_o),
        .sample_q15(sample_q15)
    );

endmodule