20 lines
469 B
Verilog
20 lines
469 B
Verilog
`timescale 1ns/1ps
|
|
|
|
// =============================================================================
|
|
// LVDS comparator
|
|
// Instantiating a spartan-6 IBUFDS
|
|
// =============================================================================
|
|
module lvds_comparator(
|
|
input wire a,
|
|
input wire b,
|
|
output wire o
|
|
);
|
|
IBUFDS #(
|
|
.DIFF_TERM("FALSE"),
|
|
.IOSTANDARD("LVDS33")
|
|
) lvds_buf (
|
|
.O(o),
|
|
.I(a),
|
|
.IB(b)
|
|
);
|
|
endmodule |