30 lines
533 B
Verilog
30 lines
533 B
Verilog
`timescale 1ns/1ps
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module sampling_tb;
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reg clk_15;
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reg clk_120;
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reg reset_n;
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sampling m_sampling(
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.clk_15(clk_15),
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.clk_120(clk_120),
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.reset_n(reset_n)
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);
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initial begin
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$dumpfile("sampling_tb.vcd");
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$dumpvars (0, sampling_tb);
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clk_15 <= 1'b0;
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clk_120 <= 1'b0;
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reset_n <= 1'b0;
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#50 reset_n <= 1'b1;
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#2000000
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$finish;
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end
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always #(500/15) clk_15 = ~clk_15;
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always #(500/120) clk_120 = ~clk_120;
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endmodule |