`timescale 1ns/1ps

module sampling_tb;
    reg clk_15;
    reg clk_120;
    reg reset_n;

    sampling m_sampling(
        .clk_15(clk_15),
        .clk_120(clk_120),
        .reset_n(reset_n)
    );

    initial begin
        $dumpfile("sampling_tb.vcd");
        $dumpvars (0, sampling_tb);

        clk_15 <= 1'b0;
        clk_120 <= 1'b0;
        reset_n <= 1'b0;
        #50 reset_n <= 1'b1;

        #2000000
        $finish;
    end

    always #(500/15) clk_15 = ~clk_15;
    always #(500/120) clk_120 = ~clk_120;

endmodule