24 lines
323 B
Verilog
24 lines
323 B
Verilog
`timescale 1ns/1ps
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module sigmadelta_sampler(
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input wire clk,
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input wire A,
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input wire B,
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output wire out
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);
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wire O;
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reg out_r;
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TLVDS_IBUF m_cmp(
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.I(A),
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.IB(B),
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.O(O)
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);
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always @(posedge clk) begin
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out_r = O;
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end
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assign out = out_r;
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endmodule |