`timescale 1ns/1ps

module sigmadelta_sampler(
    input wire clk,
    input wire A,
    input wire B,
    output wire out
);

    wire O;
    reg out_r;

    TLVDS_IBUF m_cmp(
        .I(A),
        .IB(B),
        .O(O)
    );

    always @(posedge clk) begin
        out_r = O;
    end
    assign out = out_r;

endmodule